Accurate Series Termination

I am aware that the driver output impedance or source impedance of a device may vary depending on whether it is in a high or low state. I have found that the source impedance may be as high as 200 Ohms for the logic '1' state and as low as 20 Ohms for a logic '0' state. How are you supposed to calculate an appropriate series termination when you have such a large variance in source impedance?

I assume you are supposed to calculate the series resistance from this equation:

Zt = Z0 - ZS


  • Zt = External series Termination resistor,
  • Z0 = Impedance of the transmission line, and
  • ZS = Output Impedance of the driver.

Kind Regards,
Bill Daskalakis

Thanks for your interest in High-Speed Digital Design.

Not only is there a wide variation in impedance from the HIGH state to the LOW state, but there is an even wider variation from chip-to-chip, and between manufacturers of the same chip, and over the allowed operating temperature range, and over the allowed power-supply voltage range.

The on-state output impedance of a partially-turned- on FET is very difficult to control. It depends quadratically on the exact value of the gate switching threshold, which varies wildly depending on everything else. Of course you get huge variations in the output impedance.

If you had access to +/- 20V supply rails that you could use to overdrive the FET gates in your I/O circuit (as is commonly done in switching-power- supply circuits), each FET would then turn on completely, producing an output resistance dependant on nothing but the bulk resistivity of your silicon and the size of the FET. As it is, most digital designs under-drive the gates, barely turning on the transistors, leaving the circuit quite sensitive to changes in its environment.

You also are fighting the tendency of most chip designers to make the pull-up side of the totem- pole output circuit fundamentally weaker than the pull-down side. I'm not a chip design expert, but I believe this has something to do with the superior carrier mobility available within the N-channel FET on the bottom of the totem pole as compared to the P-channel FET on the top. A larger topside FET could ameliorate the problem, but only at the expense of significant additional output capacitance (a noticeable problem in the tri-state condition).

As you have noticed, it is impossible given the specifications you have quoted to construct a series-terminated transmission line with sufficiently good termination to ensure first- incident-wave switching with a full-amplitude output signal.

If you can afford to wait a few round trip times, however, your gate performs admirably. Assuming you use transmission lines with a 65-ohm impedance, the gate output impedance will be mismatched by a ratio of no worse than 3.25:1 in either direction (either 200/65 or 65/20 equals about 3.2) producing a reflection coefficient no greater than 53 After five round-trips the residual reflection will die down to less than five percent, at which point you can safely clock the line. That's the way you are supposed to use this gate. If you can't afford to wait, you need a more accurate series termination.

What you must do to construct an accurate series- terminated configuration is use a driver with a much smaller output impedance. For example, consider the case of a driver whose output impedance varies from 1 to 10 ohms. Even though 10:1 is a huge variation in percentage terms, it is a small variation in absolute terms compared to 50 ohms. I may therefore place 45 ohms in series with this driver to produce an output structure whose impedance varies from 46 to 55 ohms, a pretty darn good match to a 50-ohm transmission line.

Alternately, you could use a current-source output circuit having an output impedance much GREATER than fifty ohms and then place an accurate resistor in parallel with the output to control the source impedance.

Either way, you end up using a good resistor to provide your well-controlled output impedance.

In the bipolar world you have other options available. For example, an emitter-follower output circuit biased with a small, but constant, output current exhibits a fairly well-controlled output impedance. ECL drivers (if properly biased) make use of this property to synthesize output impedance very close to ten ohms.

Best Regards,
Dr. Howard Johnson