Three Drop Bus

I know you are always looking for ideas for your on- line newsletter so how about this one. I have recently come across a termination suggestion, and thought you could shed some insight using your mathematically rigorous approach.

I have a 3 drop 50 Ohm bus utilizing CMOS I/O components (typical Push Pull 12ma driver). Any I/O can drive or receive, and the length of the bus is only about 4 inches. I will run this bus at ~80 Mhz and am trying to keep wire delay under 2.5 ns. My first approach was to daisy chain the 3 drops and terminate at both ends of the bus with a Thevinin termination of 330//470 (between 3.3 volts and gnd). Simulations show this meets my requirements.

The second suggested idea was to use 200 ohms to 2 volts at both ends instead of the Thevinin termination. There appears to be a power savings with this approach, but I am concerned there will be more noise induced in the power planes and packages.

Which termination technique is better?

Best Regards,
Bob Haller

Thanks for your interest in High-Speed Digital Design.

Let's generalize your problem--I think that will help you see how it works.

For the simple case of a unidirectional bus, terminated at one end, I'll compare the two different end-termination schemes you suggest:

  • (a) A split terminator, with 2R going to Vcc and 2R going to Gnd.
  • (b) A single end-terminating resistor of value R, going to a terminating voltage Vt set halfway between Vcc and Gnd.

You will note that these are exact Thevenin equivalents. The driving circuit can't tell them apart, however the POWER consumed by the two circuits differs by a factor of two.

In case (a), regardless of which way the line is driven, one resistor ends up with a full Vcc across it while the other resistor experiences no voltage drop (this assumes a perfect driver--in practice the numbers are a little different, but the same conclusions apply). The power is therefore


In case (b), regardless of which way the line is driven the resistor experiences a voltage drop of Vcc/2, so the power is...

(Vcc/2)2/R = Vcc2/(4R)

...exactly half the power dissipated in case (a).

Case (b) really does save half the power.


The power-dissipating capability of a 1206 surface-mounted resistor is only 1/8th watt (or 1/10th, depending on the manufacturer), and even less at high temperatures. The power required in case (a) in a 3.3v, 50ohm system is 0.11 watts. Smaller resistors would be inadequate for this application. For a 5-v, 50-ohm system you would need enormous 1/4-W resistors. Lower-voltage logic helps reduce the physical size of terminations. In Bob's case he apparently has enough settling time to permit use of a weaker termination (330//470 ohms), for which the power dissipation in the 330-ohm resistor is only 0.033 watts.

Further note

My power calculation includes only the power dissipated within the bodies of the termination components. In case (b) if you use a linear power supply to derive Vt you will waste an additional amount in the power supply.

P[wasted in power supply] = Vcc2/(4R)

Overall, you don't save any total system power with case (b) unless you use a switching power supply for Vt, or unless you have some other use for the current coming out of the terminators. For example, if you have a existing 2- V supply used elsewhere on the card, and if that supply can source or sink all the current your terminator throws at it no matter what, then the current dumped through your terminator into the 2-V environment is at least put to a good use.

Penultimate note

The Vt power supply must be able to both source and sink current. That is a rather unusual requirement for a switching power supply. There are two ways to meet this requirement. One way is to use twice the number of FET switches as is normally required for a source- only switching application. The other way is to build a uni-directional regulator, and apply a big dummy load (a ballast) to ensure that even when your terminator is at its worst the regulator output current never has to go negative. In this case, the ballast wastes a lot more than anything you were trying to save.

Linear regulators appropriate for the Vt application are sometimes marketed under the category of "active terminations". These parts produce a well-regulated Vt. You then tie the Vt through R to each line that needs termination, being careful to provide a bypass capacitor between Vt and Gnd at every point of usage.

Regarding general noise issues, the currents flowing in the terminators are no greater or less than the currents already flowing in and out of the power and ground pins of your drivers. If Vt is well bypassed to ground (or whatever reference plane lies underneath the traces) then there is no reason to think the termination strategy (b) will inject any more or less noise into your power system than the other style.

Final Note

Now that I've answered your power question, let me go on to recommend a structure that dissipates even less power. With three devices, if you can arrange equal lengths of 50-ohm trace between them, and if the tri-state load capacitance of the center device is small enough that it will not disturb signals passing by in front of it, then you can take great advantage of your special topology by carefully adjusting the ON-state output impedance of each driver as follows:

Three drivers connect to the same bus through series resistors.

Figure 1—This 50-ohm transmission line supports three devices.

When the left-hand device is driving the system behaves as a 50-ohm source-terminated net of length T.

When the center device is driving, the driver sees equal two 50-ohm loads in parallel (one to the right, and one to the left). The system behaves just like a 25-ohm source-terminated net of length T/2. The center driver must be located dead center in the line for this to work, and the loads must be symmetric at each end.

When the right-hand device is driving, the system behaves as a 50-ohm source-terminated net of length T.

The series-terminated nature of this structure will dissipate even less power than the end-terminated structure you proposed. One disadvantage of the three-drop bus is that if T exceeds the rise/fall time of your signals, you will notice a two-step staircase-looking waveform at the center load position. You must wait for that signal to stabilize clocking in the data.

This structure is similar to a PCI-version-I bus with the following modifications:

  1. You get to tune the impedance of each driver to best match the load it's driving,
  2. All the loads are always fixed in place (nothing is removable),
  3. There are no connectors, and
  4. You are using only the three best locations on the line: left, center and right.

Best regards,
Dr. Howard Johnson