Trace Between Capacitors

I have a question for you concerning high-speed design. A co-worker and I are having a disagreement: he says that routing traces in between pads of a surface mount capacitor is a bad idea; noise from one will couple onto the other. I say this isn't so; the current paths are orthogonal and therefore no coupling will occur. Do you have an opinion on this issue?


Thanks for your interest in High-Speed Digital Design.

Because the traces and capacitor body are at right angles there will be no net INDUCTIVE coupling between them. There will be, however, a miniscule amount of CAPACITIVE coupling.

My rough guess as to the amount of coupling is based on an assumption that the trace is 0.010" wide, the capacitor body under which it runs is 0.060" wide, and the capacitor floats above the board (on it's pad of solder) by about 0.005".

Under those conditions I would expect a parasitic capacitance of 0.05 pF (that's one-twentieth of a pF) between the trace and the bottom plate of the capacitor (in the case of a bypass capacitor this could be Vcc or it could be Gnd).

At a rise time of 1 nS (corresponding to a frequency of about 500 MHz) this coupling of 0.05 pF would have an impedance magnitude of about (1/2pi*500MHz*0.05pF)=6366 ohms. This level of parasitic coupling might introduce a 1õrosstalk into a trace of 63 ohms characteristic impedance.

Whether or not this level of coupling is acceptable depends on the tolerance of your circuit for interference. I can think of many circuits where this would not be a problem. On the other hand, it can matter a lot in some sensitive analog applications.

Best Regards,
Dr. Howard Johnson