I have a question about board level simulation of high-speed circuits. At work I often have to design test boards which might connect a DSP to an external memory or an external processor or other such device. As with all other companies, our processor speeds are increasing and that makes the interconnections more crucial. My general question is that is there a speed where it becomes foolish to try to use wire- wrap to connect two ICs together. I know that it depends from system to system, but a generalization would be appreciated. Also, what are other simple ways of connecting two ICs together that are more robust than wire-wrap? I've heard of a board to plug ICs into, which has internal switches that can be programmed to create paths from one IC to another. Are boards like this generally effective or is there another way of simply testing digital systems without having to wait weeks and pay lots of money to have the entire system fabricated?

Thanks for the advice.

Thanks for your interest in High-Speed Digital Design.

The issue with wire-wrap technology is more a question of edge transition rate than clock speed. Chips faster than about 5-ns rise/fall will exhibit some horrible ringing and crosstalk problems in wire-wrap designs. These problems can render the system non-functional.

Here’s why: with a wire-wrap design, each connection has a rather large inductance per inch, something on the order of 20 nH per inch or more.

When driving a single capacitive load of perhaps 10 pF, we get a resonance effect due to the series inductance of the wiring, and the capacitive load at the receiver. This resonance, for wires a few inches long, easily lands in the 100 MHz territory. Logic switching at a 5-nS rate contains plenty of energy in the 100-MHz range to excite these resonances, causing ringing. Slower logic doesn’t.

The ringing problem most severely affects the clocks. On the data lines, ringing doesn’t cause much of a problem, as long as your timing budget permits you enough time to wait for it to damp out before the next clock. The clock line is different. On the clock, ring-back on negative edges can easily trigger double-clocking, leading to product failure.

The general rule here is simple: don’t combine wire-wrap connections, clock nets, and fast drivers.

Assuming we fix the clocks, and further assuming that the whole board were synchronous so that crosstalk across the whole system would have a chance to settle down to zero between clocks, we could probably get a wire-wrap prototype to work at least as fast as 33 MHz, perhaps faster.

There are several solutions to the clock problem.

  1. Use a really slow clock driver.
  2. Filter the clock signal to slow it down prior to shipping it around your board.
  3. Add series terminations to the clock lines (it has to be BIG to have any effect, try 220 ohms, or even larger.
  4. Use teeny 75-ohm coax for the clock lines, with 75-ohm series terminations. Coax is available with a 0.05" outside diameter, a 30-gauge inside signal wire, and a 30-gauge drain wire, perfect for wire-wrapping.

Of course, I cannot recommend any of these approaches. I would rather see you do your functional simulation in software, but if you have already built the darn system using wire-wrap technology, those are my best ideas for getting it to operate.

Another thing some people consider for flexible prototyping is multiwire. It is kind of like wire-wrap, except that the wires are laid down by machine, pressed close down against the ground plane, and then varnished into place. This reduces the inductance of the wiring, and improves crosstalk performance. Getting a multi-wire board built is sometimes quicker than doing a regular PCB spin.

Best Regards,
Dr. Howard Johnson