I am engaged in developing a kind of set-top box. It must receive differential ECL (100K compatible) and then process it. However, I am not familiar with ECL level design. I [would like] to use a single power source (5V for VCC, 0V for GND) , so I prefer to use PECL level devices with TTL devices.

I would like to directly connect the differential ECL signal to the differential PECL device at connector point (first point) of receiver. Is this O.K., or should I use a specific level shifter circuitry or level transformer to connect them? Finally, would I need some special skill to design the connection?

Thanks for your interest in High-Speed Digital Design.

The ECL logic family was originally intended to be used with power supply voltages of 0 V and -5.2 V. The normal logic levels with ECL are:

V(OH) = -0.9 V

V(OL) = -1.7 V

The term PECL means we are using ECL logic with different power supply voltages.

The old 0-V pin connects to Vcc=+5V

The old -5.2-V pin connects to Gnd=0V

The chip is now being powered by 5.0 V +/- 10, instead of 5.2 V. Most ECL chips can tolerate this difference. The PECL logic voltage levels are:

V(OH) = Vcc - .9 V = 4.1 V nom.

V(OL) = Vcc - 1.7 V = 3.3 V nom.

Note that the PECL logic levels are now dependent on the Vcc level. As Vcc changes, the output levels change with Vcc. The common-mode input range of a PECL differential receiver will not tolerate true ECL levels (-0.9V and -1.7V).

When connecting true ECL to PECL, you will need a voltage translation.

If the data has equal numbers of ones and zeroes (for example, with a Manchester-ceded data sequence) then the level translation may be accomplished by sending the signal through a pair of DC-blocking capacitors (0.1 uF capacitors), and then re-biasing the receiver to its mid-range level. Other than this simple case, there is no good, simple way to accomplish the re-biasing.

Best regards,
Dr. Howard Johnson