Four-Way Distribution

I attended your HSDD course in March of this year at Woodline (Nortel). You may be able to remember me as the only guy in the crowd of transmission people that worked on Radio and DSP stuff.

I have a question for you and a request for advice:

I have to bring in 14 bit wide 65 MHz ADC data onto a card and distribute it to 4 separate ASIC destinations on the card. These destinations will be approximately 2-7" away (ie. two will be about 2" and the other two up to 7"). I may be able to pull some layout magic and keep the tracks all below about 4".

Data comes onto the card in differential ECL (historical) and would need to be translated to TTL/CMOS for the 4 destination ASICs. I plan to latch the data after translation to cleanup any package to package skew from the ECL-TTL translators.

The question becomes, how to distribute the data:

  1. Distribute in ECL to each destination, do local ECL/TTL translation
    CON: too much board area, power, heat
    PARTS: Motorola 10H124 10H125 diff ecl-ttl pairs
    (Which ECL family would you recommend?)
  2. Distribute in parallel at CMOS levels:
    PRO: may be smallest part count
    CON: transmission lines will result, signal integrity will be a concern. Some options require alot of packaging.
    Options within this parallel distribution would be:
    - Point to point multi-driver: dedicate 4 drivers, one for each destination and point to point them. this means a multidrop bus on the inputs of the drivers, but at least their distance would be small. I could make these 50 ohm lines source terminated as they fan out to the destinations X" away.
    - Multidrop the 14 bit bus: Have only one driver. Snake the bus to each of the destination ASICs as a controlled impedance line and parallel terminate (or end terminate with 50 ohm and 2.5 V as it is available on the card - lower power).
    - Hybrid - 2 drivers - parallel data to 2 destinations each have 2 drivers and split the 14 bit wide bus so that each drivers ships data on a controlled impedance bus to two destinations. Parallel end terminate bus.
    PARTS: For example a 74FC162374 (16 bit wide, series resistor for slew limiting register)
  3. In options 1 and 2 I would distribute the clock using a 0 delay clock buffer chip
    - for example, the Cypress CY7B9920, would AC terminate all clock lines (50 ohm controlled impedance).
  4. Distribute using high speed LVDS serializer parts from National Semi.
    PRO: small low power parts
    CON: multi-drop transmission line for the serialized data - parts were only designed for point-point but National claims that they have it working in the lab in multidrop.
    PARTS: National DS90CR215MTD Channel link parts

I would appreciate any input or thoughts that you would have.

Thanks for your interest in High-Speed Digital Design.

You should only do the translation at one point, where the signals enter the board, and then accomplish the remainder of the distribution using CMOS logic. I'm going to make this choice because CMOS is plenty fast enough to do a 65MHz uni-directional bus; using ECL with its faster edge rates would just create more headaches than it is worth.

Now, if you can arrange to have a couple of loads nearby, and a couple of loads lumped together at a distance, here is my preferred topology (please used fixed width font):


       LOAD A                                        LOAD C 
       LOAD B                                        LOAD D

Select a powerful, low-impedance CMOS driver with a risetime of about 2-3 ns. Keep the total net length comprising the DRIVER, LOAD A, LOAD B, and the SERIES-R down to 4 inches or less. The distance from the SERIES-R to loads C and D can be anything, but you will want to keep loads C and D within a couple of inches of each other. Lastly, pick the SERIES-R to match the expected transmission line impedance of the long section of the net.

I suggest you get yourself a transmission line simulator to work out the details. The general topology involving a couple of very close loads, a series resistor, and a clump of loads at the end of the line works very well.

If that doesn't work, then you should use the snaking technique you described in your message. Space the loads equally along the line, and beware that their load capacitances will add to the effective capacitance per unit inch of the transmission line. This effect will lower the effective line impedance, perhaps to a value below what you can comfortably drive with a CMOS driver and still achieve perfect first-incident-wave switching.

Best regards,
Dr. Howard Johnson