AC Coupling Layout

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AC Coupling Layout

Ray Giambi at IXIA writes:

My board incorporates a Xilinx V5 device that interfaces to a 10G SERDES. I have a question regarding AC coupling of the XAUI lanes.

I have selected 0.1uF capacitors for the AC-coupling function. My cad designer has staggered the caps on the XAUI lanes. He reasons that staggering the capacitors is better for impedance control of the differential pairs, as opposed to putting the caps side by side which separates the differential pairs.

I have not found any reference from anything you have published or from Xilinx that describes the best way to implement the capacitors in the cad layout. I believe that the best way is to put the caps side by side but I cannot support my decision to do so. I would appreciate anything you could reference or provide to support either case so that I have a better understanding on the preferred method of routing these 3GHz lanes.

Dr. Johnson replies:

Thanks for your interest in High-Speed Digital Design.

The main concern in your situation is that the parasitic body capacitance from one of the AC coupling caps to the other might perturb the characteristic impedance of your transmission line in that local region. I am not referring to the 0.1 uF capacitance from one terminal to the other of the AC-coupling component. I mean the parasitic capacitance between the body of the AC-coupling capacitor and ground, and also the excess parasitic capacitance of the capacitor's surface-mounting pads to ground.

To observe the effect of this parasitic capacitance, set up a differential TDR test. If a problem occurs, you will see a small negative reflected pulse bouncing off the AC coupling capacitors. One possible solution is to place a small hole in the reference plane underneath the mounting pads and body of each AC coupling capacitor. That relieves the excess parasitic body capacitance, fixing the reflection. On the inner routing layers of your board, don't pass any traces across this hole.  How big should you make the hole? I don't know. You'll have to experiment, either with a 3-D field solver, or by making a couple of test layouts. Something roughly the size of the capacitor body should be about right.

Mounting the AC-coupling capacitors right next to each other exacerbates the parasitic body capacitance effect (an analog designer may recognize that as a type of "Miller effect").  With the capacitors staggered, parasitic capacitance of each mounting pad and capacitor body to the reference plane still exists, but at least you eliminate the capacitance directly from one to the other.  That makes the problem a little better.

At 2.5 Gb/s per lane I think you are just on the cusp of having to worry about this problem, so staggering may help.  At 10 Gb/s I would definitely recommend the relief holes. If you do the holes correctly it no longer matters where you place the capacitors, so staggering or not it would work fine.

Whatever you choose, conduct a TDR scan of the circuit to quantify the reflections in your layout. 

Use the smallest capacitor bodies your manufacturing people will let you use. That minimizes all the parasitic effects.  You could use 0.01 uF with XAUI at 3.125 Gb/s per lane and still not get DC wander in excess of 0.1 percent (see "DC Blocking Capacitor Value,").

Best Regards,
Dr. Howard Johnson