Parasitic Pads

Code Cubitt writes:

I'm designing a 2.5-Gbps, OC-48 transceiver card. Between two chips on my board I have several discrete capacitors and resistors to slow the edges and pad the signal. It seems that the very short 1-in. trace that I'm using is covered more with part pads than with 50Ω trace. My software calculates the [trace] impedance but does not consider these parts. What effect does the pad size have on my trace impedance, and can I neglect it?

The component pads have a big impact on trace impedance, and at 2.5 Gbps, you will really notice it. The basic effect is that each pad contributes a little extra parasitic capacitance, C, to the trace. A single 1206 pad contributes about 0.72 pF (estimated at 200 pF/in.2 for 0.005-in. FR-4, ignoring fringing fields at the edges).

If you space the pads equally along the line, and if the spacing is a small fraction of the signal rise and fall time, then the parasitic capacitance of the pads merely reduces the line impedance. A general rule for the line impedance Z is:

Z =(L/C) 1/2


  • L is the inductance of the line, and
  • C is the total capacitance.

Adding parasitic capacitance increases C . According to the formula, when you increase C, you decrease Z . By whatever ratio you increase the apparent capacitance of the trace, then by the square root of that ratio, you reduce the effective loaded impedance of the structure.

The exact amount of reduction in the apparent impedance of a loaded trace is proportional to the square root of the ratio of how much capacitance would have been distributed along a raw, unloaded transmission line of the same dimensions, divided by how much capacitance you end up with after you add the equally spaced loads.

A good formula for the total capacitance, CLINE, distributed along an unloaded transmission line is:



  • T is the one-way delay of an equivalent unloaded trace, and
  • Z0 is the characteristic impedance of an equivalent unloaded trace.

If the total load capacitance added to the trace is CLOAD, you can write the impedance-reduction-ratio formula as:


If the loads are equally spaced, at least you still have a transmission line with a defined (albeit rather low) impedance. You might consider shrinking the line width to get the impedance back up to your target value of Z0.

If the loads are not equally spaced or if their spacing is too great, the signal bounces back and forth between the various capacitive discontinuities in a disagreeable manner. The worst reflection coefficient R that you can get from an isolated capacitive discontinuity in the middle of an otherwise perfect transmission line is:

R =(Z0C) / (2TR)

Where TR is the signal rise and fall time.

Closely spaced loads generate much smaller reflections.

If one section of your line has many loads, you should decrease the line width in that section to compensate but leave the line width at its normal size over the long unloaded sections.

Remember that loads sufficiently heavy to decrease the line impedance also increase the line delay. By whatever ratio the loads reduce the trace impedance, they increase the trace delay. The best way to reduce the effect of parasitic loading is to use smaller parts. The smaller the parts, the better (for example, 0603 is much better than 1206).

On a related subject, I've been told that the metallic film on most surface-mounted resistors is generally placed on only one face of the package. Such one-sided parts exhibit more parasitic capacitance to ground when turned "face down" rather than "face up." I don't think any reliable, vendor-independent scheme exists for always getting the parts turned the right way. If any readers have more information about this effect, please let me know.

Some engineers cut a little hole in the solid reference planes underneath the pads to reduce their parasitic capacitance. I am unaware of any inexpensive software or tools to help you determine the amount of cutting required, but I know microwave folks that use this trick all the time. They just try it and then adjust the hole size until it seems to work.

Full-fledged, 3-D electromagnetic-field-simulation packages can tell you what size hole to use. It seems a shame, though, to have to buy such a complicated software package and spend all that time learning to use it when you could just try a hole and see what happens. On the other hand, if you need to solve the reference-plane-hole problem many times in many situations, a good 3-D field solver could save you a lot of trial-and-error time.