Jitter-free Clocks

There are three things I've always wanted in a clock repeater: zero delay, zero jitter, and zero emissions. This combination of features would be absolutely ideal for large-system clock distribution. The first semiconductor vendor that produces such a component will be looking at a lucrative market.

The problem is, conventional wisdom says that you can have any two of my ideal features, but not all three. For example, today I can buy a so-called zero-delay clock repeater.

Such a part incorporates PLL technology. The part has one reference clock input and multiple buffered clock outputs. The internal PLL continuously monitors the relation between the phase of the input reference clock and the phase of the outputs. The PLL then adjusts the output transitions so that they land precisely on top of the input transitions within a tight timing window—perhaps as small as 50 psec. The input-to-output delay is, effectively, zero. With sufficient power-supply filtering, the zero-delay part can also produce very low jitter.

What this part does not do is generate zero emissions. The continuous, harmonic structure of the clock creates huge peaks in the emission spectrum (at multiples of the clock frequency)—the kind of huge peaks that keep EMC engineers awake at night.

How about using a spread-spectrum clock? A spread-spectrum clock is frequency-modulated, so that its center frequency undulates back and forth around a nominal value. The intentional jitter, or frequency wander, in a spread-spectrum clock tends to smear the spectral peaks. The resulting spectrum has peaks in the same positions, but they are broader and lower. In the limit with extreme amounts of frequency smearing, the peaks almost disappear. The spread-spectrum idea gets you the zero-emissions property but blows it on jitter. You cannot easily interface a spread-spectrum clock to any normal communications device that requires a steady, jitter-free frequency reference. This deficiency, in my opinion, limits the applicability of spread-spectrum clocking.

Is there any way to make a timing reference that has low jitter and low spectral peaks and at the same time is compatible with zero-delay-repeater structures? Yes. One solution to this problem is a well-established, mature technology in current production. Engineers just haven't applied this technology to the clock-timing problem on pc boards.

The solution is a scrambled clock; that is, a digital signal with transitions at fixed integral points in time but with random HIGH or LOW transitions at each point. Think of it as a serial data-communications signal with pseudorandom data. The PLL circuit you need to recover the clock from this pseudorandom data stream is not that much different from the PLL circuit in an ordinary zero-delay clock repeater.

jitter free clock If you have concluded that the zero-delay repeater is a good thing, then the extra circuitry that a zero-delay scrambled repeater requires is trivial.

Scrambling smears the spectrum much like spread-spectrum frequency modulation, but with one key difference: The clock edges remain fixed in precisely quantized positions. Therefore, jitter on the recovered clock is very low.

A pseudorandom sequence only 256 bits long breaks the clock spectrum into 256 individual peaks, each of which carries approximately 1/256 of the full clock energy, for a peak spectral-power reduction of better than 20 dB.

Let me point out a few other tricks you'll want to use if you start working with scrambled clocks. First, you want to standardize the pseudorandom clock so it is predictable. This step simplifies the design of the PLL recovery circuit. Second, with a sequence of length N, you may use a simple divide-by-N counter to produce a frequency reference precisely locked to the incoming clock rate. On power-up, this reference jump-starts the PLL. Such an "acquisition aid" significantly reduces the lockup time. Finally, you want a sequence with a high rate of transitions (simplifying the PLL filter circuits) and with an equal number of ones and zeros (making possible some neat tricks for dc-level restoration and duty-cycle compensation).

If you work for a semiconductor company, I hope you take note of this concept. Scrambled clocks significantly improve radiated emissions without adding jitter.