Backplane Design

I have been doing high-speed-board designs for several years and now am working on a backplane design for the telecomm business. The power source to our equipment pro-vides -48V and -48V RETURN, which must be bused to all the line cards that plug into the backplane. On each of the line cards, I have an isolating dc/dc converter to step down from -48V to 5 and 3V. Many 1.25-Gbps differential signal pairs go across the backplane between the line cards. My questions are:

  • Should I use dedicated power planes for the -48V/-48V RETURN supplies on the backplane?
  • Should my differential striplines be referenced to the -48V/-48V RETURN planes?
  • If I reference my striplines to the -48V/-48V RETURN planes, how do I deal with any noise on the -48V supply?
  • What are the advantages of using edge-coupled rather than broadside-coupled layout? I have nearly 750 differential pairs at this speed. The overall board thickness is a concern.

When you say your dc/dc converters are "isolated," I assume you mean that the -48V/-48V RETURN connections bear no dc relation to the 5V, 3.3V, and ground terminals you use to power the cards. Such a power supply will work well in your application.

An isolated supply does not require solid -48V/-48V RETURN connections on the backplane. You can implement the -48V/-48V RETURN connections with fat traces. This approach saves some space in the layout. Use 2-oz copper on the -48V layer if necessary or whatever it takes to carry your dc current without objec-tionable dc voltage drops. Alternatively, you may want to bolt metal bus bars on the back of the motherboard to carry the heavy currents. Metal bus bars con-sume zero layout area in the motherboard, and the power cables can bolt directly to the bus bars.

Within the motherboard, incorporate a number of solid planes connected to chassis ground. Call these layers chassis_A. These planes separate the routing layers. for crosstalk control. All traces are therefore referenced to the chassis ground. Also put a solid chassis_A plane on both outside layers of the mother-board. Expose a strip of the chassis_A plane all around the edge of the mother-board and bolt this strip directly to the product chassis, using plated holes that connect all the internal chassis_A layers. Connect all the chassis_A planes with a virtual sea of vias on a regular grid. Use a grid spacing that is smaller than your signal rise and fall times.

To the extent that your differential drivers are not perfectly balanced, the chas-sis_A layers may be carrying some substantial fast transients. Therefore, the chassis_A layer at points internal to the motherboard is not at the same potential as the external chassis. If your cards require a "quiet" chassis connection-for example, to use for lowpass filtering of I/O signals exiting the box-you should prepare a second chassis layer, chassis_B. Layer chassis_B connects to the product chassis at its edge but is not otherwise connected to chassis_A, and you must not use it as a reference plane for any fast digital signals. You can use a completely separate layer or an isolated section of one of the chassis_A layers for this purpose.

Practical rather than electrical considerations determine the choice of edge-coupled (side-by-side) versus broadside-coupled (over and under) differential-stripline pairs. Broadside coupled traces suffer from a slight asymmetry that oc-curs when you couple from the surface of the board down into the routing layers. This asymmetry arises from the fact that one signal via must penetrate more deeply into the board than the other. Broadside coupling also requires supertight board-fabrication tolerances because you must fabricate the two elements of each pair on different layers.

To avoid the asymmetry and tolerance problems, I like to use edge coupling with the following board stack: A-S-S-A-S-S-A-S-S-A. This stack has four chassis_ A layers (A) and six signal layers (S). It provides three routing cavities, each con-taining two signal layers. The signal layers within each cavity comprise a horizon-tal-vertical routing pair. The three horizontal routing layers that carry your 750 pairs sideways across the backplane must endure a worst-case density of 250 pairs (500 wires) per layer. A 9-in.-high backplane would require a line density of 55 wires/in. for an average line-to-line pitch of 0.018 in., a generous allotment.

A standard 0.096-in.-thick motherboard with this layer stack will provide 30 mils of vertical space within each cavity. Within each cavity, you can use 6-mil traces with 8 mils between the elements of each pair, spaced 7 mils above the nearest reference plane. This geometry produces a differential impedance of 100W. Use a pair-to-pair spacing of 16 mils for a total differential-to-differential-mode crosstalk of about 2.

Your situation sounds manageable with edge-coupled pairs, and I would try that approach first.