Asymmetric Noise Margins

Is the following reasoning correct?

Logic-high signals have a higher noise margin than logic-low signals, thus, they do not need the same amount of noise protection on the rising edges. Therefore, the fall time and not the rise time affects ground bounce. By slowing the speed of the falling edge, you can reduce signal ringing and ground bounce.—Ming Xu

I will direct my comments toward the most common case: ordinary CMOS chips driving source-terminated (or unterminated) transmission lines. In that case, your statements are true for 5V CMOS circuits using TTL levels. Your statements may be true for other logic families, depending on the logic levels and style of termination you use.

When using 5V TTL levels, a source-terminated CMOS driver puts out 0V for logic low, whereas the required 5V TTL-low input level is specified at 0.8V. The difference between what the driver puts out and what the receiver needs (0.8V) is the chip's tolerance for ringing, crosstalk, and other noise. This tolerance is called the low-side noise margin.

The same 5V CMOS driver switched high puts out 5V, whereas 5V TTL-level inputs require only 2.4V for reliable switching. The noise margin on the high side is 2.6V. In this scheme, the high state tolerates much more noise than the low state.

Extreme asymmetries such as this one create a preferred logic level. Referece [1] suggests that when designing a system whose logic levels lie at rest most of the time, such as an interrupt signal line, you assign the preferred logic level to the at-rest condition.

The signaling asymmetry is particularly pronounced when you use source-terminated CMOS logic to drive 5V TTL-style inputs. For 3.3V logic, the voltage margins are much better balanced between high and low states. The same goes for many lower voltage logic families.

Ground bounce, which is nothing more than noise on a chip's internal ground rail, mostly involves how quickly you change the current flowing through the chip's ground connections. Noise on the internal VCC rails within a chip involves how quickly the VCC currents change. Slowing the rate of change of either current reduces the noise on the affected internal power or ground rail.

When dealing with source-terminated drivers, ground currents flow through the chip only during a brief interval as each line is pulled low. These currents result from the discharge of the line capacitance through the chip's I/O cell to the ground. When switching a source-terminated line high, power-supply currents similarly flow through the chip only for a brief interval. With source-terminated drivers, the switching speed in the low direction controls the magnitude of the internal ground bounce, and the switching speed in the high direction controls the magnitude of the internal power-system noise. Because the NMOS half of a typical totem-pole driver usually sinks more current than the PMOS half, source-terminated configurations often generate more internal ground noise going low than going high.

When you are dealing with end-terminated transmission lines, the situation changes. A split terminator at the end of a transmission line (R1 to VCC and R2 to ground) continuously sinks current while holding low. Such a load generates two ground bounce events each cycle. First, when driving low, the sinking current turns on; then, when driving high, the sinking current turns off. Either way, a sudden change in current occurs. Both transitions create a pulse of ground bounce that, if sufficiently large, can generate transitory input errors. The same thing happens on the power rail.

Whether your circuit responds more to ground bounce or internal power-rail noise depends on how your chip derives its internal reference voltage. The comparator circuits inside the chip use the internal reference voltage to discriminate between high and low inputs. Noise on the reference appears, for all practical purposes, the same as noise directly on the inputs.

TTL-style inputs are designed to operate at the same switching threshold regardless of the value of VCC. These inputs develop their input reference a fixed number of millivolts above the internal ground substrate. Therefore, noise on the internal ground substrate directly affects the reference voltage, which in turn affects the inputs. These ground-referenced inputs are more susceptible to noise on the chip's internal ground rails than on the internal VCC rails.

PECL (positive emitter-coupled logic), on the other hand, uses the more positive power rail to derive its internal receiver-reference voltages. PECL inputs are, therefore, more susceptible to noise on the internal power rails than on the internal ground rails.

In light of this discussion, I shall now recast Ming Xu's question to read, "Does the low-side noise margin of a ground-referenced chip driving a source-terminated (or un-terminated) line benefit from slowing the falling edge rate of the drivers?" The answer is yes.


[1] Buchanon, James, Digital Signal and Power Integrity , McGraw-Hill, 1995, ISBN 0-07-008734-2.