Slow wave mode

The slow-wave effect hampers signal transmission on some on-chip MIS (metal-insulator-semiconductor) interconnections. On such interconnections, the substrate resistance adds substantially to the signal loss and can sometimes have the peculiar effect of greatly slowing signal propagation. The resulting slow-wave mode occurs when you adjust the substrate conductivity so that electromagnetic fields only partially penetrate the substrate. The wave velocity then becomes a function of the substrate—not just the good dielectric insulation between the trace and the top layer of the substrate.

Figure 1 illustrates a classic on-chip MIS transmission line, comprising a metal trace, a 1-micron silicon-dioxide insulating layer, and a 200-micron semiconducting substrate. The solid metal layer on the back of the substrate is called backside metallization. In this example, assume a worst-case value for the conductivity of the silicon-substrate layer, about 50 S/m. At a frequency of 1 GHz, the intrinsic impedance η and skin depth δ of the substrate are:


  • ε0εr,substrate represents the electric permittivity of the substrate (F/m),
  • μ is its magnetic permeability (H/m), and
  • s is its conductivity (S/m).

At 1 GHz, the low intrinsic impedance of the substrate (12.6Ω) prevents electric fields from easily penetrating it. However, magnetic fields permeate the entire substrate because the skin depth (2.25 mm) greatly exceeds the thickness h2. Because the electric fields are virtually stopped at the upper substrate boundary, the transmission line inherits a capacitance in accordance with the small distance h1 between the trace and the top of the substrate. The complete penetration of magnetic fields implies an inductance in accordance with the much larger distance h2 to the bottom.

This circuit suffers from a physical separation of the electric and magnetic fields. In a perfect, homogeneous dielectric material, with a uniform conductor, the electric and magnetic fields penetrate to the same depth, and the propagation velocity equals (εμ)–½

In Figure 1, a different effect comes into play. The electric fields penetrate only to a depth of h1, while the magnetic fields penetrate much further, all the way down to h2. That combination disconnects the homogeneous assumption. The resulting combination of big capacitance (from the shallow electric-field penetration) and big inductance (from the deep magnetic-field penetration) creates an absurdly slow velocity of signal propagation, something much slower than the permittivity of either the insulator or the substrate alone would indicate. Furthermore, the complicated frequency dependencies associated with the slow-wave effect create significant phase distortion in the received waveform.

To fix the problem, you have three choices (Reference 1):

  1. Raise the substrate conductivity by doping until it acts like a good, low-impedance return path. This approach shrinks the skin depth, forcing currents to flow mostly near the top surface of the semiconducting substrate. The line delay then depends only on the permittivity of the insulator (about 4.0 for silicon dioxide).
  2. Decrease the substrate conductivity by doping until it acts like a good, high-impedance insulator. The electric and magnetic fields then completely simultaneously penetrate the substrate layer. The line delay in this case then depends mostly on the permittivity of the substrate (about 12.0 for lightly doped silicon). A high-speed chip requires backside metallization for this approach to work.
  3. Add intentional metallic return paths near the signal traces.

The conductivity of pc boards is so low that the boards effectively adopt the second configuration. For the second approach to work, the board must incorporate a solid-metal reference plane in the layer stack. The reference plane serves the same purpose in a pc board as the backside metallization in a chip—it defines a good return-current path for all signals.

Occasionally, a board designer implements the third choice. For example, in a 100BaseTX interface between the isolation transformer and the RJ-45 connector, you might use a co-planer differential pair with no underlying reference plane. The differential pair comprises a signal trace and an associated return-current conductor, so it meets the definition of the third option.

The only way to separate the electric and magnetic fields on a pc board is to implement a nonuniform trace. For example, attaching hundreds of little crossbars (like cilia) to a pc-board trace adds substantial amounts of capacitance without changing the inductance, creating an absurdly low impedance and high delay.


[1] Ashok K. Goel, High-Soeed VLSI Interconnections, John Wiley & Sons, Inc., 1994.