Data Coding for Low Noise

Differential-I/O configurations can substantially reduce power and ground noise internal to an IC [1],[2]. The resulting circuits require fewer power and ground pins than might otherwise be necessary. Unfortunately, differential signaling doubles the number of I/O drivers, BGA balls, and pc-board interconnects.

Specialized data codes can reduce power and ground noise without doubling the number of interconnects. A data code judiciously assigns to each M-bit binary word a unique binary pattern (a code word) that it selects from a larger field of N-bit possibilities, in which N is greater than M. Each individual code word has a weight, w, which equals the number of ones in that word. For an N-bit word, the possible weights range from zero to N.

Associate professor MR Stan of the University of Virginia's Electrical and Computer Engineering department investigated limited-weight data codes in 1995. His bus-invert code appends one extra bit to each data word x according to two simple rules[3]:

  • If fewer than half the bits in x are 1, append a final 1, producing [x:1]
  • Otherwise, invert x and append 0, producing [x:0]

Any input word with weight of less than M/2 triggers the first "IF" clause, adding one to the weight. That scenario produces weights ranging from 1 to M/2. Otherwise, the inverting clause converts words of weight w into words of weight M-w. That translation maps all ones (weight M) to all zeros (weight 0), and a word of weight M/2 (right at the decision boundary) to a different word also having weight M/2. The net result is that the inverting clause produces a range of weights from 0 to M/2. Compared with the full input-weight range of 0 to M, the output weight now varies over a range only half as great.

In any code, the maximum code-word weight bounds the number of high or low transitions that can occur between code words. The half-size maximum code weight of the bus-invert coding, therefore, cuts in half the number of simultaneously switching outputs, thus halving all your worst-case I/O-related power and ground noise problems. Stan originally developed his coding ideas for reducing on-chip power dissipation, but the same concept works wonders for reducing power and ground bounce[3].

Be careful with weight calculations. A change in weight does not indicate which bits have changed. The change in weight indicates only the aggregate number of high transitions not counterbalanced by opposite transitions somewhere else. To be specific, going from weight 2 to weight 3 may mean that one new bit went high, or it could be that two bits went low, and three others went high.

Some data codes produce code words within a restricted range of weights. Such codes cleverly counterbalance each low transition with a high transition that resides elsewhere within the same data word—a quasi-differential mode of signaling. Real differential configurations counterbalance each low transition with a high transition on an adjacent wire. Restricted-weight data codes counterbalance each low transition with a high transition that resides elsewhere within the same data word. Applying a restricted-weight data code to a bus would reduce noise in a way that is similar to differential signaling, but with fewer interconnections.

For example, the 4B/5B code popularized in fiber-optic versions of FDDI (fiber-distributed data interface) and Fast Ethernet synthesizes one extra bit for each four-bit group in a data sequence. The resulting 5-bit code words all weigh either 2 or 3 bits, so no more than one unbalanced transition ever occurs from one code word to the next. A 32-bit bus that you implement as eight independent 4B/5B groups produces a maximum of eight unbalanced transitions between successive 32-bit words. That number is one-fourth the amount of unbalanced transitions that an uncoded 32-bit bus could produce.


[1] Johnson, Howard, "On-chip bypassing with series termination," EDN, April 29, 2004, pg 24.

[2] Johnson, Howard, "On-chip bypassing with end termination," EDN, May 27, 2004, pg 22.

[3] Stan, MR, "Bus-Invert Coding for Low-Power I/O," IEEE T VLSI SYST, March 1995, Vol 3, pg 49.