It's HOT here in the Cascade Mountains of Eastern Washington State, and somewhat SMOKY. I live near the Tripod Fire complex, a large wildfire that, according to government bureaucrats, exhibits "active fire behavior". Really? I would say it exhibits, "Entire mountaintops covered with 200-foot flames, enormous choking columns of smoke rising to the stratosphere, a deafening, thundering roar, and 100,000 acres of wilderness completely reset to the Stone Age."
The Tripod fire ignites the hills East of my home (2006).
More than 2500 firefighters work on the blaze full time, with more arriving daily. Mostly what they do is—you'll love this—set more fires. Each day the firefighters set a series of well-controlled, can't get out-of-hand, government-sanctioned fires in a ring around the burning area. This strategy pre-burns the available fuel ahead of the main conflagration, leading to its eventual demise. Is that a cool job or what? You get to set forest fires on purpose, and you get paid for it. Experts predict that, "At the current rate of resource utilization, the fire will be completely contained by November."
I predict something different. I predict that if we keep sending pyromaniacs up in the hills with matches, you'll be able to see our entire mountain range glowing from outer space by next Thursday.
In the mean time, I hope it doesn't come any closer.
As long as we are discussing fire, and I assume that at least some of you share my professional fascination with the subject, let me pass along these words of advice from my friend Bernard Hosey, "Do not let anyone incinerate your laptop in a huge fireball like this.
Memory Bus Crosstalk
Pete Atkinson writes:
I am currently working on a project that has a high speed memory bus. We have a significant amount of “interconnect jitter”. My memory team is recommending that we change the bus geometry to improve timing. I’ll try to give you the lay of the land:
We currently have a 4 layer bus, outer layers are signal, inner layers are GND on L2 and PWR on L3. My memory bus is split referenced, routed on L1 and L4. The L1 signals are GND referenced, the L4 signals are power referenced. I have ~4.3mils between L1 and L2; a thick core; then 4.3mils between L3 and L4. My current geometry is 4-9-4 (4 mil trace, 9 mil space, 4 mils trace).This is supposed to yield a 60 ohm single ended impedance.
The memory routing is cramped, so we cannot increase the total area that the routing consumes by much. My memory team is recommending we go to a new geometry that is 8-5-8 (targeting 45 ohm single ended impedance).
The theory is that a lower impedance trace will exhibit less impedance variation from x-talk. Seems reasonable. However, the effects of the reduced spacing on the lines effects the x-talk by a square term, whereas the larger traces effect the mutual capacitance and inductance linearly. I would expect that the x-talk would become more dominant (over impedance) the closer the lines get. Initially, the recommendation was even more aggressive: 9-4-9. When I started asking questions, they quickly backed off to 8-5-8 (I was worried about the manufacturability of a 4 mil space between 9 mil traces, which they bought). I am still concerned that their claim that the lower impedance is dominant may not be correct.
Oh yeah, the bus is 750MHz GDDR3. The rise times are pretty fast, I think along the lines of <200ps (not 100% sure here). I would like to have a little better understanding of x-talk vs. impedance before I spend time and $$ to build this and test it.
Thanks for your interest in High-Speed Digital Design.
You have asked a simple question, and it deserves a simple, straightforward answer. Figures 1 and 2 show the results using Hyperlynx Linesim for your two most extreme cases, 4-9-4 (63 ohms) and 9-4-9 (42 ohms). The simulations show both near-end and far-end crosstalk (NEXT and FEXT) for the three nearest neighbors.
NOTES: I did not change the termination impedances to perfectly track the varying line impedances in this experiment. For the duration of the exercise, all signals were terminated in 50-ohms to ground at both ends. No solder mask is used. The aggressor is driven with a step voltage of approximately 2.3 volts in every case, with a 50-ohm end-termination. The driver source impedance is fixed at 5.0 ohms.
As you can see in the following table, assuming that the overall trace pitch remains fixed, the lowest crosstalk is obtained using the narrowest traces with the highest-impedance. The theory about low-impedance traces picking up less crosstalk would apply ONLY if the mutual capacitance were fixed, independent of spacing. In your case, as you bring the traces closer together, the capacitive coupling grows faster than the impedance drops.
|Trace geometry||delta-V||NEXT||NEXT %||Z0|
The above table shows NEXT only; the FEXT behaves in a similar manner. It is worse in the 9-4-9 layout. Depending on your exact termination arrangement, the receivers could end up with a total crosstalk equal to the sum of absolute values of both NEXT and FEXT.
In a working system I usually expect that a crosstalk coefficient of, say, 9.0 percent will modulate the received edge transition times by about 9 percent of the signal rise or fall time. You can use this rule of thumb to estimate the jitter you expect to receive as a result of calculated crosstalk.
Keep in mind that the table shows only the near-end crosstalk from one nearest neighbor. In a real system, each trace receives crosstalk from a number of neighbors on both sides. The worst-case crosstalk under multi-aggressor stimulation for this bus will be about three times bigger than the single-aggressor numbers shown in the table.
Crosstalk in digital systems is a little quirky, because of the directional nature of the crosstalk effect (see Directionality of Crosstalk ../straight/crosstalk.htm). As a result of this directional effect, a system with terminations at both ends of the transmission line (this may not be feasible for your memory architecture) enjoys a unique crosstalk advantage: the near-end crosstalk never finds its way to the receivers. If you use a stripline architecture (this may not be feasible for your 4-layer design) there is practically no far-end crosstalk. Combining these ideas, a double-end-terminated stripline suppresses both the NEXT and FEXT mechanisms, producing the quietest, most densely-packed structure we know how to make. It is possible that your board designer is trying the mimic the trace-packing density he or she may have observed in some system that uses double-end terminated striplines. Your system, with single-end terminated microstrips, cannot be packed as densely.
Instead of changing the trace geometry, how about using a thinner dielectric layer? A 3-mil dielectric layer, as opposed to the 4.3-mil layer in your present design, gets the traces down closer to the reference plane so they interact more with it and less with each other. That change combined with the 4-9-4 layout gives you 53-ohm traces with 25% less crosstalk than anything else in the table. Spreading the traces also helps dramatically.
One fact you may have left out of your thinking is the effect of the layer change from 1 to 4. At that point on the board, power-supply noise extant between the planes enters your memory-bus circuit traces. This may be a major source of crosstalk, depending on the efficacy of your power-supply bypassing. Has anyone looked at the level of noise on the memory traces that jump layers, versus those that remain on layer 1? Excessive power supply noise at the jump location could completely swamp out the differences in crosstalk due to trace layout.
Penultimate comment: The raw impedance of your unloaded traces is much different from the loaded impedance of your traces once you include the capacitance of the receivers. If you start with low-impedance traces, the receiver capacitances may drop the impedance of the whole arrangement so low that your driver will be unable to produce full-sized waveforms.
Last thoughts: You need a signal integrity simulation tool. Get one.
Dr. Howard Johnson