Greetings everyone! This summer found me busy working on some projects that I hope will benefit you and your co-workers.
In my last letter I mentioned the extraordinary week I had at the University of Oxford in June. High-Speed Digital Engineering Week brought together several of the world's best-known experts in signal integrity, EMC and High-Frequency Measurement for a week of seminars, panel discussions, and student interaction. The event was open to all professional engineers without regard to prior affiliation with the University.
If you ever wanted to try out a signal integrity course, Oxford is a great place to do it.
Squeeze Your Layer Stack
I used to not worry about adding layers to a backplane; as long as my fabrication shop could build the board it didn't much matter. Now, working at speeds well in excess of 1 GHz, my attitude has changed. At high speeds, backplane thickness becomes a matter of performance.
Figure 1 charts the S21 transmission coefficient of a typical through-hole (press-fit) backplane via, assuming a backplane thickness of 250 mils and a dielectric constant of 4.30 at 1 GHz. This chart assumes a worst-case configuration for signals traversing the via, namely, that the signals enter from the press-fit connector pin on the layer-1 side of the board, and dive only down to the first (nearest the surface) stripline layer. That assumption leaves the bulk of the via body dangling, unused, below the active current-carrying portion of the via structure.
The red dotted line illustrates the S21 transmission coefficient you would measure when sending data through such a via, taking into account only the total capacitance (2.4 pF) of the via structure and assuming the entire capacitance acts as a single, lumped-element component. As you can see, the total capacitance of a via accounts of some, but not all, of its transmission characteristics. The actual performance is substantially worse that you would predict based on capacitance alone.
The complete transmission curve (solid red) incorporates the series inductance of the via. The path of current flowing through the capacitance of the via must traverse the via itself, then flow as displacement current through the parasitic capacitance of the via to the various solid planes within the board, and then finally make its way back to the surface of the board near the point where the via impedance is measured. This circuitous pathway engenders some amount of inductance, producing a circuit that acts much like a capacitor (the parasitic capacitance of the via, Cv) in series with an inductor (the parasitic series inductance of the via, Lv). You may remember from circuit theory that such a configuration forms a resonant circuit with a zero in impedance located at this frequency:
That point (about 5.5 GHz) is indicated in Fig. 1. This zero in the transmission response, by the way, shows up in fullwave 3-D field solver plots of dangling vias and also in actual measurements—it's a real effect—but in a slightly different location than given by the simple approximation for F0.
Any portion of your signal that has significant spectral content at frequencies approaching F0 will be severely distorted passing through this via structure. Even at 2 GHz, well below F0, the via attenuation is 2.5 dB, a noticeable (and objectionable) amount.
The green curve represents the improvement possible with a better backplane material. In this case I selected a Taconic TLE-95 material with a dielectric constant of 2.95. This material reduces the dielectric constant by a factor of 2.95/4.30, producing two beneficial effects. First, holding all other physical parameters the same, the reduction in dielectric constant directly reduces the parasitic capacitance of the via by the same ratio.
In addition, the reduced dielectric constant also renders feasible a reduction in trace height (Figure 2). Keeping the trace width constant, the new dielectric constant permits a board stack 30thinner than the original. The original and modified layers stacks are shown in Figure 2. Squeezing the layer stack shortens the backplane vias, again reducing parasitic capacitance (good) and also reducing their parasitic inductance (also good).
Other ways to reduce the size of your backplane vias (and thus their parasitic effects) include backdriling, and the use of blind or buried vias combined with surface-mounted connectors.
Dr. Howard Johnson