It's a beautiful blue-sky day here at the ranch.
The snow is just melting off the hills and the
songbirds of spring are starting to re-appear after
a long winter.
I read your article on Fiber Optic encoding where you explain about DC balance in different encoding schemes and in the latter half you explain about SONET data which is scrambled and how many long run's of 0's & 1's it can have.
I use SONET scrambled data on backplane and statistically the length can be 72 0's or 1's but in SONET frame the J0/Z0 byte is not scrambled, so the user has to stuff this byte with enough transitions otherwise the run length can be very high. Still, with min 72 I think AC coupling will be a problem.
Why? Because the DC level could drift depending on the run length of 0's & 1's and this could cause EYE closing at receiver and hence increase BER. Is there a solution to this if a user has to use AC coupling? Also, does the capacitor need to be of microwave quality which has resonance above the Fknee frequency?
Thanks a lot.
Thanks for your interest in High-Speed Digital Design.
Regarding your inquiry, the DC balance of SONET can be terrible. If I understand your description of the coding correctly, you can get a run of 72 1's, followed by a couple of transitions, followed by 72 MORE 1's, etc. There's no good, cheap way to AC couple such a system. Any linear circuit you apply is subject to the statistical possibility that the AVERAGE DC level might go to 1 (or 0) and stay there long enough to defeat your circuit. You are therefore relegated to using some form of non- linear DC level restoration.
Figure 1 shows one way to build a non-linear DC restorer. The circuit in figure 1 assumes the signal has been AC-coupled at some point prior to the terminating resistor RT, stripping the signal of all low- frequency information. The purpose of the circuit is to restore the lost low-frequency components of the signal.
The circuit incorporates two filters, a high-pass filter F and a complementary filter 1-F. The input passes through F, to a SUM circuit, then on to the slicer and sampling register. The sampled output is fed back through (1-F) to the SUM circuit.
The concept behind this circuit is that whatever DC information is lost by F is made up by feeding back the slicer output through (1-F) to the summation node.
The circuit in figure 1 realizes the circuit concept using one capacitor and one resistor. The capacitor implements high-pass filter F, while the resistor implements (1-F).
This circuit requires that you first terminate your input and buffer it with a low-impedance linear driver.
If you know a little about analog filter design you can check that the circuit correctly implements the filters. It does a good job provided that the output impedances of the buffer and the sampling register are really low, and the slicer input impedance is really high.
As long as the time constant R1*C1 is much shorter than the time constant of any AC coupling network that precedes the buffer, the circuit will properly restore your signal at the input to the slicer. An advantage of this circuit is that it does not require high tolerances on the AC coupling capacitors that precede RT, nor on C1 or R1. This is a very old circuit concept. It is used in (among many other places) some Fast Ethernet 100 Mb/s transceivers.
I like this circuit better than systems that differentiate the incoming signal and then fire "set" and "reset" operations based upon the appearance of either positive or negative pulses in the differentiated signal. The differentiation circuit is extremely susceptible to high-frequency noise and it requires multiple slicer levers. The approach in figure 1 adds only a low frequency, very clean signal to your received data and therefore (theoretically) has almost no impact on noise performance.
Dr. Howard Johnson