I would like to know which is the best way to measure Signal jitter using a Digital Oscilloscope.
Here's my situation:
- An Hsync signal is fed to my system from a VGA cable.
- There is a PLL clock generator in my system.
- I want to measure/characterize the jitter coming out of the PLL clock generator.
What type of jitters can be measured using what types of oscilloscopes and how should one go about it?
Thanks for your interest in High-Speed Digital Design.
There are (at least) three jitter measurements that might interest you:
- [A] The jitter transfer function (that is, how the PLL amplifies jitter present within the Hsync signal),
- [B] The power supply sensitivity of the PLL (that is, how the PLL amplifies jitter arriving through its power supply terminals), and
- [C] The intrinsic residual jitter (noise) from the PLL circuit itself.
A full model of the PLL noise output combines all three effects. Before I describe the measurement techniques in detail, let me make a general point about the relative difficulty of these three measurements.
Measurements [A] and [B] are made by injecting a known disturbance into your system and observing the result. In the test setup for [A] and [B] you have the freedom to inject a rather large disturbance, which simplifies the measurement task (because you will be looking at a big result). Measurement [C] will be more difficult, because you will be observing very tiny amounts of phase modulation, and it may be difficult to determine the source of the noise.
Now let's go on to the details. To measure [A], you need to generate a fake Hsync signal. The fake Hsync signal is phase-modulated with an adjustable sinusoidal source. Call the modulation rate "MR", and the modulation amplitude (in peak-to-peak radians) "MA". Many high-quality RF signal- generators can be FM-modulated (or PM-modulated) in this way and used as a fake Hsync source. While you apply the fake Hsync signal, observe the PLL output with a scope. If the PLL produces a high multiple of the Hsync clock rate, you might want to use a divide-by-N counter to reduce the PLL output to a more manageable frequency. Set the scope to trigger on the PLL output, delay by 1/2 the period of the FM modulation (that's 0.5/MR), and then display the PLL output.
If the modulation frequency is low enough for the PLL to track it, any modulation in the Hsync input will appear directly in the PLL output. Using a horizontal time-base delay of (0.5/MR) you will see the displayed edge switch at a range of times corresponding to the maximum peak-to-peak phase modulation amplitude (MA) of the fake Hsync source.
If the modulation frequency MR is high enough that the PLL filters it out, the display will appear rock-steady.
At intermediate frequencies, you may find a large peak in the PLL transfer function (a place where the ratio of output phase deviation to input phase deviation exceeds unity). Good PLL circuits don't have such a peak. The location of the cutoff between the tracking frequency and the filtering frequency, and the magnitude of the intermediate peak (if any), together constitute a good way to characterize the PLL JITTER TRANSFER FUNCTION. This function is usually plotted on log-log paper showing the jitter transfer function (ratio of output phase deviation to input phase deviation) as a function of frequency.
To measure [B], you will make a test much like [A], but instead of modulating the Hsync input, this time you will modulate the PLL power-supply voltage. Do this by injecting sinusoidal noise directly onto the Vcc terminal of the PLL. If there is more than one Vcc input, then test each input independently. If your circuit incorporates a good power supply filter that prevents you from injecting noise into the Vcc terminal of the PLL, remove some of the bypass capacitors on the PLL side of the filter until you are easily able to inject substantial amounts of noise. AC-couple your sinusoidal source to the Vcc terminal of the PLL.
While you apply sinusoidal Vcc noise at frequency F and amplitude X, observe the PLL output with a scope. As before, set the scope to trigger on the PLL output, delay by 1/2 of the period of F, and then display the PLL output. I like to do this test starting with F below the tracking bandwidth of the PLL, and sweeping up to somewhat beyond the PLL output rate. At each frequency F, adjust the scope horizontal time-base delay to match 0.5/F, and then tweak the amplitude X of the sinusoidal Vcc noise until you get a standard amount of objectionable phase jitter in the output. You can use any standard objectionable output jitter level, perhaps 0.1 times the output clock period, or some other amount that you suspect might begin to cause a problem. The amount you set as your standard objectionable level should (hopefully) be large enough to easily measure.
I then make a plot showing, as a function of frequency F, the maximum amplitude X of Vcc noise the circuit can tolerate before the output jitter comes just up to the objectionable level. You may combine this basic data with another plot that shows how much noise is already present in your power system as a function of frequency to tell you how much power supply filtering you will need, and what must be its frequency response. This is the only rational way I know to actually DESIGN a power filter for a PLL.
To measure [C], you can try using the scope to make phase-deviation measurements at various delay intervals, but the results will likely be unsatisfactory. Measurements [A] and [B] are easy to make because you are injecting a HUGE phase deviation (perhaps as much as 0.1 bit interval or more), and the resulting phase jitter is easy to see. For test [C] you need an instrument that can measure tiny amounts of jitter. Use either a timing interval analyzer, or a spectrum analyzer. Either can be used to make a measurement of the total variance of the total phase deviation. When you make this test you will want to carefully filter the PLL power supply, and use an ultra-clean, low- jitter Hsync clock, to eliminate noise from those two sources so you can see the remaining, intrinsic noise of the PLL circuit.
Dr. Howard Johnson