I have a number of high-speed differential PECL signals that I need to route in parallel on the PCB. Routing space is an issue, so ideally, minimal trace separation is desirable. The board is 10 layers with the following stackup:
1 components and signal 2 --------------------- plane 3 signal 4 --------------------- plane 5 +A+ +B+ +C+ 6 -A- -B- -C- 7 --------------------- plane 8 signal 9 --------------------- plane 10 components and signal
+A+ and -A- (and B and C) are the differential pair traces (one on top of the other). The distance between the (+) signal layer and the (-) signal layer is 8.5mils. The distance from top plane to (+) signal layer and bottom plane to (-) signal layer is 6 mils. The worst case situation is to assume that A and C are the aggressors on B the victim.
If A, B, and C were not differential, the "3 times rule" would imply a trace spacing of 3*6=18mils to achieve a crosstalk factor of 0.1 (using K=1/[1+(D/H)^2] calculation) from A to B and from C to B. However, I believe that since the aggressors are differential, most of the E field will be cancelled and the crosstalk factor would increase much more rapidly with trace separation D.
Do you agree? What would the K calculation be for this topology?
Thank you very much.
Thanks for your interest in High-Speed Digital Design.
While it's true that two widely separated differential trace pairs on a PCB will have very little crosstalk, the differential approach is practically useless when the traces must be closely spaced. Here's why:
Crosstalk falls off very rapidly with distance. For closely spaced traces, the crosstalk from +A+ to +B+ is MUCH stronger than crosstalk from -A- to -B-.
To give you a sense of what might work in your application, I ran your configuration through a 2- dimensional field calculator from Hyperlynx and came up with the following numbers. All cases assume the use of source-terminated, 3.3-V differential drivers and receivers. The distance between the (+) signal layer and the (-) signal layer is 8.5mils. The distance from top plane to (+) signal layer and bottom plane to (-) signal layer is 6 mils. Ignoring trace thickness, that makes a total cavity height of 20.5 mils, as in your example. The trace width is 7 mils.
If you are working with a bus, remember to add crosstalk from your two nearest neighbors, plus a little from the next two traces over.
If you want to compute these answers yourself, look into the software tools available from Mentor, Cadence, Veribest, and Hyperlynx (among others). They have done a lot of work on differential trace impedance lately and all have ways to directly compute the crosstalk for your configuration.
Oh, as a little bonus, I calculated one other configuration. In this new layer stack, I kept the same overall thickness, but pushed the trace layers apart, moving each signal layer closer to its respective reference plane. The distance between the (+) signal layer and the (-) signal layer is now 12.5mils. The distance from top plane to (+) signal layer and bottom plane to (-) signal layer is 4 mils. Ignoring trace thickness, that makes the same total cavity height of 20.5 mils, as in your example. To make this work, I used a trace width of 5 mils.
|13 mil||220 mV||143 mV|
Dr. Howard Johnson