I would like to put forward the following for your opinion:
In our designs, we have been using the approach of connecting the capacitor to PWR/GND pins of the IC on one side and to PWR/GND planes on other side. The length of trace connecting capacitor to the IC pin is generally very small (50 - 80 mils) and PWR/GND vias are placed very close to the capacitor pads. In some cases, where it is not possible to place the capacitor parallel to the side of IC, capacitor is placed perpendicular with one side of capacitor connected to PWR pin of the IC and the other pin going directly to GND.
In my opinion, one main advantage of this approach is that only two vias are needed instead of four and that saves routing space on the board. Also, very little inductance is introduced due to small traces.
I may add here that I had two boards constructed using the two different approaches and I didn't notice any significant change in the emission profile between the two boards.
In a paper presented in the IEEE EMC Symposium, 1996, the author described a new approach to bypassing. It described use of buried capacitance (power and ground planes stacked together) as the primary bypass capacitor and evenly spaced capacitors to replenish the charge of this primary capacitor.
In this approach, all PWR/GND ins of the ICs are directly connected to the respective planes. I would like to know your views on this method of bypassing. While on the subject of bypassing, I often find it difficult to calculate the number of bypass capacitors and their values for a particular application.
Section 8.2 of your book describes the method of calculating these values but these calculations result in a large number of capacitors for the values 1000pF/1500pF used in our designs. I am further confused when I see that most designs of Fibre Optic communication circuits with data rates of over 1 Gigabit/sec show 0.1 uF bypass capacitors in use, whereas I believe these capacitors may not be effective over 10 MHz.
I will appreciate if you can help clear my doubts.
Thanks for your interest in High-Speed Digital Design.
Let’s see what I can make of your many different issues.
First, your assumption that the little traces in your layout are insignificant is just plain, dead, wrong. Please let me explain.
The most important parameter of a bypass capacitor is its impedance at high frequencies. To see why, think about the kind of noise you typically see on Vcc. Do you see a lot of power supply noise in your systems at 1 MHz? Big, slow undulations in the Vcc supply with time periods of 1 uSec or more? No, probably not. What you likely have (as do we all) is noise in the 100 MHz and higher region. That's the "problem zone" for most power supply systems. In the problem zone most bypass capacitors will be operating far above their series resonance point. That is, they will be acting like little inductors, not little capacitors. Their impedance will be heading up (+20 dB/decade) and their phase angle will be +90 degrees (current lags voltage). Please don't be alarmed. Operating above series resonance is perfectly OK, AS LONG AS THE INDUCTANCE IS SUFFICIENTLY LOW.
That brings me to an important point. The single most important specification for a bypass capacitor is its series inductance.
And, you may know, for surface-mounted bypass capacitors the effective series inductance is controlled by only two factors: the body size, and the layout.
The body of any 1206 capacitor (if perfectly mounted over a solid ground plane) only contributes about one nanohenry. The layout can contribute a lot more. Just as a crude guesstimate, the vias together contribute about one additional nanohenry. The traces contribute about 1 nH per 100 mils of trace.
Your layout has maybe 80 mils of extra trace on either side of the capacitor, for an additional 1.6 nH. Your installed total effective inductance is therefore 3.6 nH, compared to the 2 nH I get when I lay out the parts correctly. When I connect a chip to the planes, and separately connect the capacitors to the same planes, I am, in effect, using the planes themselves as huge, fat, perfect traces to connect the chip to its capacitors. That's a better deal.
I'll cast my vote for the style of layout you saw at the IEEE EMC Symposium (whether or not I use a special high-dielectric material between the power and ground planes). The chips should connect straight to the planes. So should the capacitors.
Now, about your emissions performance. It's great that you are OK on emissions performance. You've told me that your capacitors are connected to the planes with vias connected "very close to the capacitor pads". This is (apparently) controlling the overall Vcc-Gnd noise, which is one of the factors that can cause a lot of radiation if done improperly. So far, this is all good news. The one aspect of board performance that I would like to suggest you investigate (not because you are saying it is a problem now, but because it will become a problem as you go to higher and higher-speed designs) is ground bounce. When your chips blast out a lot of current to a big load, look at where that current flows, and how it returns to its source (see also Vol 2, Number1). First, the signal current goes to the load, following the traces you have provided for that purpose. Then, it passes through the load into the power/ground system. Finally, it must get from the power/ground system back to the power or ground pin of your driver. To make this last leap, in your design, it has to traverse a via, go across the surface of a bypass capacitor pad, and then through another (80 mil) trace to get home. I think you've certainly added some extra inductance in this path. It is the inductance of this path that creates ground bounce. If you reduce the inductance of this path (by connecting the chip power/ground pins straight to the planes) you will see less ground bounce. Take the time to characterize how much you have today, so that you don't get into trouble with this layout style in the future.
Last point--let’s think for a minute about the value of capacitors you are using.
Yes, it's true that their series resonant point is higher than that of a .1 uF bypass capacitor in the same package. But, if your parts and the .1 uF parts are in the same package, then the effective series inductance, the single specification that defines the performance of these parts at high frequencies, is the same for both parts. You are buying no increase in high-frequency performance, and a big disadvantage at the low end (witness how many parts you have to put on the board to meet the low-frequency constraints in your system). For our high-speed, digital, bypass application, once you have chosen the package size and the layout, buy the biggest valued capacitor you can reliably procure that fits in the package.
Dr. Howard Johnson