When trying to match flight times across a set of signals, vias become an impact to the total delay seen through the trace compared to a trace with no vias and having an equivalent length.
One method of dealing with this is to add "dummy" vias, which are not used to transition between layers, but only to add extra delay. But while the dummy via may have the same amount of capacitance as the real via, it does not necessarily have the same effect on the flight time as a real via. Can you recommend a way to calculate the delay through a real via vs. a dummy via in the case of a 4-layer board?
Dr. Johnson replies:
Thanks for your interest in High-Speed Digital Design.
I wish I knew the answer to your question. I don't think anybody does. If you are working with extremely fast signals (less than 300 ps edges) you'll want to think about the impact not only of the vias, but of the return path for your signaling current. If your trace jumps from one position adjacent to Vcc, through a via to another position adjacent to Ground, both the position of nearby bypass capacitors and the interplane spacing will affect the overall inductance of the return path. Inductance in the return path has the same effect on delay as inductance in the main path. In other words, for vias which traverse several planes, the delay is a function not only of the via but also of the position and configuration of nearby bypass capacitors.
For vias, which merely penetrate a single plane (that is, the signal trace crosses from one side to the other of one solid plane), the return current path flows easily from one side of the plane (directly underneath the incoming trace), through the clearance hole in the plane to the other side, and then continues underneath the trace as it exits the via. (The planes are many skin-depths thick, so the current does not penetrate the planes.) The cool thing about this arrangement is that is does not depend on any bypass capacitors! Therefore, the delay experienced in this configuration will be more predictable, and more repeatable, than with the multi-plane-penetrating via. It's OK if the via hangs down through several planes, as long as the signal path just goes from one side of a solid plane to the other.
For vias which penetrate a single plane, my prediction is (and this is merely a prediction, not a measured fact) that these vias act mostly as a simple capacitive load. Therefore, for traces routed on either side of a single solid plane, the inclusion of matching vias should work quite nicely.
Dr. Howard Johnson