Hello Dr. Johnson--
Members of our company attended your seminar, which you taught in house last year. Since I have seen many questions that you have answered, I thought of sending you one that concerns one of our company's design 'standards'.
In our design standards for low EMI design techniques, one [topic] is covered that is not exactly clear how it might actually help. The topic concerns segmenting the Vcc plane. I will quote from the 'manual':
"The component layout becomes less critical if we use another method of keeping the RF voltages on at least that part of the Vcc plane supplying the sensitive circuits at a minimum. By cutting the Vcc plane into segments, where each segment RF-isolates the several circuits being fed by the segment, the bouncing of the Vcc plane outside of this segment will be reduced as a function of the effectiveness of the means of isolation used. It is important to understand the difference between the 0-volts plane, which must not be divided or segmented under any circumstances, and the Vcc plane, for which proper segmenting can improve the EMI characteristics."
An illustration of the approach shows several Vcc plane segments interconnected by ferrites (inductors). This seems somewhat distasteful. Is there any truth to the claims made by this approach? In the past the designs I have been involved with have always attempted to use solid copper planes for providing low inductance pathways for the device supplies, and appropriate decoupling capacitors for the devices. If there were analog circuitry that might be sensitive to noise present on the supply rails, these were fed by separate dedicated power planes. The previously quoted technique was derived at empirically, are there any analytical results that can explain what was claimed to have been observed?
Thanks for your interest in High-Speed Digital Design.
I like the solid-Vcc plane method best. I don't cut up the Vcc plane unless I have one circuit that is substantially more sensitive to Vcc noise than the other circuits on the board.
I've seen companies that go to an extreme with the Vcc isolation idea. Sometimes they will provide a separate Vcc patch for every chip on the board. Such extremes are not necessary (unless you have chips with radically differing noise sensitivities).
Connecting together all Vcc sections actually REDUCES noise across the board. Here's why:
First, imagine that within every section, we have loaded the board with enough bypass capacitors to limit the peak noise in that section to precisely 200 mV. All sections have the same peak amount of Vcc noise.
Now, connect two adjacent sections. If they have the same, identical noise waveforms (amplitude and phase), then connecting them together will do NOTHING (i.e., no current will flow across the gap). This is a pretty unlikely scenario.
If, on the other hand, the two sections have different Vcc noise waveforms, then current will flow in a manner which tends to AVERAGE the noise voltage between the two sections.
In other words, connecting the two sections NEVER HURTS, and it has the benefit of REDUCING the peak noise excursions.
In terms of worst case design parameters, we have just reduced the peak worst-case Vcc noise. Your chips will thank you.
My rule is simple: All chips using the same logic levels, with the same noise immunity, are tied together to a pair of solid Vcc and Gnd planes.
Dr. Howard Johnson
P.S. - your EMI friends may want to think about the effect of routing traces on layers adjacent to their cut-up Vcc plane.
Traces passing perpendicular to the Vcc cuts produce classic "slot antennas", which are known sources of horrible emissions, and also serve to couple together the Vcc regions, subverting the "isolation" that was supposed to exist between regions.
With today's fast logic and big busses, you can't really expect to contain high speed noise to a region surrounding the driver. The outgoing signal traces propagate the noise to the far corners of the board.
To get their isolation idea to work out, you'd have to have a rule that said to never use any layer adjacent to the cut-up Vcc plane for trace routing.