Ten Layer Stack

I am currently designing a board with 10 layers (six signal, two ground, one +5 volt and one +3.3 volt) and want to know if the 3.3 volt plane can be considered a valid reference plane for signals that are not driven by the 3.3 volt devices? Especially 5 volt signals routed next to the 3.3 volt plane near the backplane connector.

Stack up:

1 Signal
4 Signal
5 Signal
6 Signal
7 Signal
8 3.3v
10 Signal

Thanks, Bill Noonan

Thanks for your interest in High-Speed Digital Design.

To find the answer to your question, let's do an example. Note that I have labeled your layers 1-10, from top to bottom.

In this example we will trace the path of signal current as it leaves the driver, as it travels around the board, and as it returns to its source (remember that current always makes a loop). To begin, we will use one particular PCB trace. Suppose this trace starts at point A on layer 1. From there the PCB trace leads 6 inches along layer 1 to a via at point B. From point B we drop down to layer 7 and then continue, going 6 more inches to the destination at point C.

     driver (A) --<6 inches, L1>-- via (B) --<6 inches, L7>-- (C)

Obviously, on the way to the load, the signal current simply follows the PCB trace. The path of current as it makes its way from the load back to the source is not so straightforward. As a general rule, the returning current always wants to flow on whatever plane is nearest to the outgoing signal trace, following along directly under the signal trace. Given a way to do so, it will always take that path. This is a GOOD THING, because to the extent that we can cause return current to flow nearby the outgoing signals, we have controlled crosstalk, reduced EMI, and (for reasons you will understand in a minute) lowered the power and ground noise on the card.

One exception to this rule occurs near the driver. At the driver, there are two possible paths for returning current. The returning signal current can enter the driver chip either through the chip’s Vcc pin, or through its ground pin. When the chip is driving high, returning signal current always enters the chip through the power pin. . When the chip is driving low, returning signal current always enters the chip through the ground pin. Either way, at this point the returning current has been diverted away from the main flow of signal current.

Now let’s track down the precise flow of returning current in our example.

During the first nanosecond after an initial rising edge (the propagation time from (A) to (B)), the return current is building up on layer 2, flowing under the outgoing signal trace. It flows (first) through the Vcc pin of the driving gate to layer 3, (second) through a 5-v bypass capacitor from there to layer 2, and (then) along the top surface of layer 2, underneath the signal trace.

At via (B), the signal trace dives down through the layer stack, and then runs adjacent to layer 8. The returning current must find a path from the top surface of layer 2 to the top surface of layer 8. The path it selects will be: (first) along layer 2 to the nearest 3.3-v bypass capacitor, (second) through the 3.3-v bypass capacitor from there to layer 8, and (then) along the top surface of layer 8, underneath the signal trace. In other words, when we route 5- v signals on a layer adjacent to the 3.3-v plane, we end up pumping a lot of big, bad 5-v signal currents through our 3.3- v bypass capacitors. That’s not such a great idea, if you can avoid it. The result will be: more crosstalk between the 5-v and 3.3-v segments of the system, and more power-supply noise on the 3.3-v plane. These effects may be counteracted by adding more 3.3-v bypass capacitors to the board.

I hope this brief analysis has helped you understand that we need bypass capacitors in three places:

  1. (1) near all drivers
  2. near all vias
  3. near all receivers (to convey parasitic receiver currents to the correct plane)

In each case, the function of the bypass capacitors is to provide opportunities for returning signal currents to flow from plane to plane, in those instances where it needs to do so.

I can't know if this will work for you, but a lot of people faced with a similar situation would divide the card into two regions, one for 5v and one for 3.3v, and use this stackup:

1 H-Signal pair A
3 V-Signal pair A
4 H-Signal pair C
6 5v AND 3.3v split plane
7 V-Signal pair C
8 H-Signal pair B
10 V-Signal pair B

I've denoted horizontal and vertical routing layers with the terms H-Signal and V-Signal, respectively. I've also paired the planes together, suggesting that when possible, the router try to keep a trace that starts on layer 1 confined to only layers 1 and 3. Similarly, layers 8-10 are another routing pair, as are layers 4-7.

Pair A and pair B are the two best routing pairs in this design. That's where you should route your highest-speed stuff. Example: when a trace routes from layer 1 to it's pair partner, layer 3, the return current need only flip from the top side of layer 2 to the bottom side of layer 2 (this is easy, because the plane is perforated with many, many holes). This is an ideal signal propagation arrangement and will result in the lowest crosstalk, EMI, and power/ground noise. In those cases where a trace must jump from pair A to pair B, the return current can flow through vias (not bypass capacitors), because the layers 2 and 9 are at the same potential, and are tied together (hopefully) with lots and lots of ground vias.

The disadvantage of this layout is that high-speed traces routed on layer 7, if they cross the split-plane boundary, will be susceptible to crosstalk (because their return paths must divert through 5v bypass capacitors from the 5v area of layer 6, down to layer 5, and back up through 3.3v bypass capacitors to the 3.3v area of layer 6).

This is similar to the diversion you had in your original stackup. The difference is that those sorts of problems now occur only on layer 7, whereas in your stackup the return current diversion problem will affect more of the layers.

Lastly, you will notice that I have carved the board stackup into sections of no more than two signal layers, running at right angles, between planes. This is good for crosstalk control.

I hope these pointers will be helpful to you.

Best regards,
Dr. Howard Johnson