In your high-speed digital design class, I recall that you suggested an AC-biasing scheme like that on p. 238 of your book (section 6.4.2) for PECL differential pair signals. I also remember you saying that the capacitor (C1 in Figure 6.11) should be tied to Vcc since the PECL reference voltage is most closely related to the Vcc plane.
Assuming I am remembering correctly, I am now wondering how this type of termination works. Specifically, I thought that PECL outputs always need external resistors to ground since PECL drivers can only source current but not sink it. Where is the path to ground when the capacitor is tied to Vcc?
Thanks for your interest in High-Speed Digital Design,
Your description of the circuits at the **end** of the line is correct: a resistor from each line to a common node (A), and a capacitor from (A) to Vcc.
What's missing is the circuits that must go near the driver to bias the ECL outputs into their active operating region. For PECL, this would be a 330-ohm resistor from each output to ground.
Sounds like I left that part out in our class discussion -- guess I was assuming everyone always did the 330's to ground.
An alternate way to bias the drivers is to hang a third resistor from node (A) to ground. Properly calculated, it will draw enough current from both lines to keep the outputs happy.
Dr. Howard Johnson