In 1965, Gordon Moore, chairman emeritus of Intel, foresaw, "The doubling of transistor density on a manufactured die every year." His based his prediction on the rate at which he believed the IC industry could develop and deploy successive generations of semiconductor processing equipment. Moore later modified his prediction to a doubling every eighteen months, which is what we know today as Moore's Law.
In hindsight, this rule has proved remarkably accurate. Not least among the reasons for its accuracy is the aggressive pace set by Intel in its quest to build ever-more-powerful ICs.
In other industries, such a fast pace of development would be unimaginably difficult to achieve. For example, if the automotive industry achieved similar rates of progress, today you would be driving disposable cars that cost less than a penny, weigh less than a gram, and get better than 41 million miles per gallon. Sound impossible? Of course, but for semiconductors, such development is natural. Manufacturers of integrated circuits expect their chips to shrink every year. As they shrink the size of their circuits, they also reduce the inherent parasitic limits to speed, enabling incredible advances in the speed of operation.
Every three years, the Semiconductor Industry Association (SIA) publishes an industry road map, showing the consensus view of expected developments in chip performance. In its most recent report, the SIA predicts that by 2009, DRAM chips will hold 64 billion bits of information, processors will clock data at 6000 MHz, and ASIC packages will bristle with 4000 connections.
These predicted improvements in chip-level performance sound fabulous, until you consider what happens when people like me agglomerate many chips into a system-level product. The problem is that the chips are getting faster at an exponential pace, while the performance of the packaging hasn't kept up. Mathematically, unless the packaging performance can increase along the same exponential pace as the chips, the packaging will eventually become a serious impediment to overall system performance. That's happening right now.
I don't mean to suggest that we chip slingers have been resting on our laurels; but really, I can count on the fingers of one hand the number of big, widespread, popular advances in system-level packaging in the last 20 years. Multilayer pc-boards, solid power and ground planes, surface-mount technology, reflow soldering, and the BGA package were the prominent advances. These advances have been nice, and so far, they have been enough to keep ahead of the chip industry, but these basic techniques aren't going to last much longer. To fully realize the benefits of faster chips, here's what will be required:
- Better packages, with less ground bounce and crosstalk,
- Better control over Z0, with greater circuit density,
- Better, cheaper terminations,
- Lower-voltage signaling,
- Better-controlled rise times,
- Better probes,
- Better tools for signal-integrity management, and
- More engineers who understand transmission lines, ringing, ground bounce, crosstalk, and EMI.
Such development is a tall order, but those of us building large-scale digital systems cannot get by with less. If we follow through on all points, we can expect to keep up with Moore's Law for a long time.