The circuit in Figure 1 includes a plethora of termination options. The figure shows four results using various combinations of component values, each observed at the point indicated by the purple arrow.
In the first three results, resistor R2 is replaced with a 0O short, and resistor R3 is not installed. This is a classic series-terminated approach using only resistor R1, having values of 33, 18, and 4.7Ω, respectively.
Looking at the rising edges, the signal in each case fails to achieve full strength on the first stroke, as indicated by the “plateau” marking on each waveform. In each case, subsequent reflections at 2-nsec intervals push the signal voltage up toward its 3.3V limit. As the value of R1is successively reduced, the first stroke becomes more powerful, climbing higher toward the goal of first-incident-wave perfection but never quite achieving it. Even with R1 set to 0Ω, this driver will never achieve perfection when driving a 50Ω line, because the effective driver output resistance, RS, is greater than 50Ω.
The falling edges tell a different story. With R1 set to 33Ω, the initial drop in the falling waveform is 2.7V—a larger step than the first step in the rising waveform. That clue tells us the driver output resistance in the falling direction must be less than the output resistance in the rising direction, a common situation in CMOS totem-pole drivers. In the third waveform, by the time R1 is set to 4.7Ω, the signal undershoots significantly. The driver in this case is too powerful.
If your driver output resistance varies between its rising and falling edges, as it often does, then no value of series-terminating impedance can possibly make both edges perfect—but perhaps you can make it better.
A higher value of line impedance helps. To see why, suppose that your driver has output resistances of 60 and 37Ω in the rising and falling directions, respectively, as in this example. Mate that to a transmission line with a characteristic impedance of 10,000Ω using a series resistor of 9,951Ω. The effective impedances in the two driving directions are now 10,011 and 9,988Ω, respectively—very close matches to the line impedance.
Of course, you can’t make such a circuit, but even raising your transmission- line impedance to 65Ω permits a higher value of R1, making R1 a more significant part of the circuit and thus reducing the impact of variations in the natural output resistance of your driver.
A slower edge helps. The signal rise and fall time now is about 1 nsec. Some FPGA drivers have a facility for slowing the edge-transition time, which would be ideal. If you don’t have that, try inserting a damping resistor R2=50Ω or more in series with the receiver (fourth waveform). That additional resistance, working into the 9-pF capacitance of the receiver, forms a lowpass filter that can lengthen the edge-transition times, reducing the amount of undershoot in the falling direction and making the waveform less sensitive to natural variations in the driver’s output impedance.