The recent IEEE CPMT (Components, Packaging, and Manufacturing Technology Society) meeting in Portland, OR, produced a plethora of papers documenting interactions among system architecture, signal quality, RF interference, power-system noise, thermal dissipation, size, weight, cost, and numerous other factors. Here's a sampling of subjects that keep those folks up at night:
The concept of dissipating 2700 Watts in a highly packed mechanical structure;
That the complexity of a problem described in its raw geometry is, for the purpose of modeling, overwhelming;
The nonlinear effects of the noise interaction between simultaneously switching noise, common-mode noise, and crosstalk; and
The uncompromised modeling of the power grid during switching (references 1 through 4, respectively).
All those interactions have me concerned. In simpler times, a system designer could separately select a power supply to crank out some amps, a fan to remove the heat, a processor and auxiliary components to do the work, and a little software to make it all useful. Designers independently tackled each design discipline—power, thermal, hardware, software—with its own engineering budget and its own design margin. No longer.
In today's tightly packed designs, everything interacts. The next chip you add might produce too much crosstalk, block the airflow for other chips, or overload the power supply. If you squeeze out that last drop of performance by turning up the clock or adding one more feature, you risk choking on the curse of complexity—at which point every decision you make interacts with every other decision.
Suddenly, it seems no one can accomplish advanced design without simultaneously considering all factors at once, engineering the electrical, mechanical, thermal, RF, EMC, ESD, software, user interface, and end-of-life recycling policy all in one stroke. This principle, taken to an extreme, limits the development of high-end products to a few well-capitalized companies that can afford to create their own tools for managing the increasingly awesome degree of design complexity necessary.
We have stood at this crossroads before. In the last instantiation of the "everything matters" crisis, the designs were called supercomputers. Anybody remember Amdahl? How about Cray? Both pushed their supercomputer designs to the utmost limit of technology available at the time (bipolar, ECL). They employed relatively large engineering staffs that spent a great deal of time developing meticulous models, advanced design tools, and beautifully integrated designs, but relatively less time thinking carefully about what their customers needed and how to implement features and services that would knock down the competition. The competition, it turned out, was not IBM at all; it was the lowly PC and the local-area network.
Some designers believe CAD tools will save us. With enough software, they believe, you can manage integrated electro-software-mechanical-thermo-radiation problems of any complexity. I do not think so. I think that when designs stretch so close to the limit that everything matters all at once, then the engineering process becomes so complex and takes so long to execute and test that the process accomplishes little of real value.
Comparable historical trends toward design complexity occurred at the end of the era of relay logic, then again with tubes, then with discrete transistors, and finally with bipolar ICs. In every case, the end-of-life scenario for each generation of technology included a great deal of work on integrated design rules and processes. The purpose of these rules and processes was to manage the increasing complexity of working with devices stretched to the limits of their capability. CMOS logic now suffers the same fate.
If you believe that history repeats, prepare now for the next generation of technology. What it will be, I have no idea, but I do know this: To work at higher frequencies, the packages must be fundamentally smaller than those we have today, and the design rules must be easier to swallow.
Note: All references are from the proceedings of the IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging, Oct 25 to 27, 2004.
 Patel, P, et al, IBM BladeCenter System Electrical Packaging Design Challenges, IEEE cat# 04TH8772, pg 11.
 Buris, Nicholas E, Electromagnetic Modeling as a Constituent of Multi-Disciplined Design, pg 35.
 Deutsch, Alina, et al, Methodology to Simulate Delta-I Noise Interaction with Interconnect Noise for Wide, On-chip Data-buses ..., pg 295.
 Jae-Yong-Ihm, et al, Modeling of Semiconductor Substrate on On-Chip Power Grid Switching, pg 265.