A robin builds her nest in the spring. An astronomer turns his gaze to the heavens on a moonless night. A marksman pulls his trigger in the brief moment of rest between the beats of his own heart.
In all these things, there is a cycle of time. Each cycle holds moments both good and bad for various events. Understanding precisely when to act is important in all three cases.
The same logic applies to a digital state machine. There is a good time and a bad time for a chip to sample its digital inputs.
Consider the case of a simple synchronous state machine with one common clock. You've probably noticed that the most noise occurs when the outputs are changing. The outputs usually change right after the active edge of the clock. Therefore, the quietest part of the cycle occurs almost one full clock interval later, right before the active edge of the next clock. In the instant just before the clock, noise from the previous pattern of output transitions has undergone almost one full cycle of decay.
If you are using edge-triggered flip-flops, the moment of relative quiet just before the next clock is precisely when each latch samples its inputs. Perfect! This fortuitous coincidence of timing confers a great natural noise immunity upon all synchronous, edge-triggered digital state machines.
The only input left unprotected by timing is the clock itself. The clock, an asynchronous input, remains susceptible to noise at any time. A glitch at any moment sufficient in size to cross the input threshold of the clock receiver can cause double clocking, destroying the integrity of the state machine. You can easily remedy this special sensitivity of the clock by implementing differential clock inputs. A good differential clock input rejects noise on the external power rails as well as any internal ground bounce (or VCC bounce) generated within the chip package.
When you equip an ordinary synchronous ASIC with a differential clock, you substantially improve its immunity to internal ground bounce. You may therefore put that part in a less expensive, smaller package with fewer power and ground pins than would otherwise have been required.
The moment you add a second, non-synchronous clock to an ASIC, the noise situation significantly deteriorates. The two clocks may phase themselves such that when the circuits associated with one clock create their maximal noise, the circuits associated with the other clock are trying to sample their inputs. Non-synchronous clocks impair the natural immunity of synchronous operation. Here's what you can do to regain the lost noise immunity of a double-clocked ASIC:
- Use a more expensive chip process with separate I/O power rings to isolate the interfering circuits,
- Add more power and ground pins to reduce the general level of internal simultaneous switching noise,
- Use a package with less ground-lead inductance per pin,
- Slow the I/O drivers,
- Drive fewer or lighter loads, or
- Reduce the noise budget elsewhere to make up the deficit.
Any way you look at it, the second clock complicates the picture. From a noise perspective, the fewer places in which multiple clocks coexist, the better.
If you are testing a system with multiple clocks, make sure you test them in a truly asynchronous mode. To simplify the test setup, test engineers often lock all the clocks together. This procedure is fine for initial functional testing, but it does not represent a worst-case test of noise immunity. For worst-case testing, you must allow the phase of each clock to precess with respect to the others. To guarantee a minimum rate of precession, you can offset the main reference oscillator for one clock by soldering an extra capacitor to its crystal.
With the input clocks precessing at their maximal rate, your system should function with no errors. If you'd like to further stress-test the system, you can solder extra capacitors across the output pins of each ASIC. These capacitors increase the local current required of each output, exacerbating the internal ground bounce. Expect a robust system to tolerate at least 2 and perhaps 10 pF of additional capacitance without complaint. If it doesn't, you have a good indication that the circuit is close to the edge of its tolerance for additional noise.
Equipping one ASIC with two non-synchronous clocks is the practical equivalent of asking an astronomer to look at the stars in broad daylight. With enough engineering you can make it work. (Witness the orbiting Hubble telescope.) But it's a lot easier if you look only at night.