In my last column, I presented a rather troubled system architecture with incredibly stringent signal-quality requirements. The signal source is a low-impedance ECL driver with a 400-psec rise time, which connects to the receiver by 3 ft of RG58 A/U coaxial cable.
Somebody else already built the signal source, so you are stuck with the low-impedance ECL output. By government contract, you must design the receiver using an off-the-shelf FPGA combined with an external 50±1-Ω terminating resistor.
So far, the termination strategy sounds good, but unfortunately, the FPGA has a 9-pF input capacitance (Figure 1). When it connects directly to the external 50-Ω end-terminating resistor with R2=0 Ω, the input capacitance interferes with the operation of the termination, creating massive reflections. The reflections return every 8 nsec, commensurate with the round-trip delay of the coaxial cable.
Quantifying the impedances in this circuit, the 400-psec rise time corresponds to a frequency of roughly F= 0.35/(400 psec)=875 MHz. At that frequency, the 9-pF capacitance of the FPGA inputs presents an impedance magnitude (1/(2πFCIN)) of just 20 Ω. This low impedance loads the 50-Ω termination, preventing the terminator from doing its job.
Now, insert resistor R2with a value of 50 Ω in series with the FPGA input. This circuit trick raises the effective input impedance of the FPGA to something at least 50 Ω or greater. In the worst-case scenario, if the capacitor impedance were absolutely zero, the parallel combination of R1 and R2 would make a termination impedance of 25 Ω, creating a reflection coefficient no larger than one-third.
Resistor R2 acts as an isolation component, preventing the FPGA capacitance from directly loading the terminating resistor. A value of 50 Ω for R2 in this circuit yields a fourfold reduction in the reflected signal amplitude.
At the same time, resistor R2 degrades the received-signal rise time. This situation occurs because the combination of R2 and CIN acts as an RC lowpass filter. Setting R2 equal to 50 Ω in this circuit doubles the signal rise time.
If you are worried about late reflections shifting the apparent times of arrival for subsequent edges, the induced jitter varies in proportion to the product of the reflected signal amplitude (as a fraction of the signal swing) times the signal rise time. If the reflections decrease fourfold but the rise time doubles, then you win a twofold reduction in jitter. That outcome is good, but I want to do better.
In my next column, I will show you how to force the termination impedance to equal exactly 50 Ω with minimum degradation of the received-signal rise time.