Did the US Congress appropriate $94 million, or was it $94 billion, for the Department of Agriculture in 2005? Who can remember? To most people, all big numbers sound the same, so they care little about the difference. Besides, if the amount ever causes a problem, Congress can always legislate a bigger debt ceiling to work its way out of difficulties.
A similar psychological effect pervades the world of tiny numbers—humans amalgamate all diminutive quantities into a single concept of "small." I regularly observe this effect when asking an engineer, "What is the rise time of your signals?" Clearly, the answer is small, but when put on the spot, some people are unsure whether the measurement of this rise time is in picoseconds, nanoseconds, or microseconds. Do you know the exact value of your rise time? I cannot imagine any more important question with which to begin the analysis of electrical-circuit behavior.
The ratio of signal rise time to physical delay in an electrical circuit determines how the circuit behaves. A small ratio, meaning a short rise time compared with the innate time delay of the circuit, produces distributed behavior. The other possibility, a large ratio, invokes lumped-element behavior. In both cases, the relative comparison of the rise time with the physical extent of the circuit determines behavior, not the absolute value of either quantity.
You need to know whether your circuit is distributed or lumped, because distributed systems sometimes display wiggly, undulating waveforms. They respond differently at different points and may exhibit severe resonances. On the other hand, lumped-element circuits more often work in an easily understood manner. You can describe lumped-element circuits using simple circuit schematics, and you can quickly simulate them in Spice.
For example, consider a thick FR-4 backplane with press-fit connectors. The vias in this design have a barrel diameter of 0.035 in. and a length as great as 0.250 in. You can calculate the raw, unloaded circuit delay for signals moving through such vias as (½-in. length)×(180 psec/in.)=45 psec.
In an old 33-MHz backplane-transceiver application (that is, BTL/Futurebus), assuming rise and fall times of 2 nsec, the ratio of rise time to via delay is inconsequential. At such a slow speed, you can model these backplane vias as simple lumped-element devices—usually shunt capacitances. In addition, because the via capacitances are not very great (2 pF), such vias work fine on a 33-MHz bus with 2-nsec rise and fall times.
A serial application running at 10 Gbps presents an entirely different story. The bits in this application fly by 300 times faster, with correspondingly smaller rise and fall times. A factor of 300 is huge. In such a fast system, a via delay of 45 psec can easily exceed the signal rise time. Thick backplane vias at this speed respond in a highly distributed fashion and can become significant problems.
When considering any aspect of your circuit geometry, the relation between physical size and rise time helps determine the relative importance of that object in the overall scheme of the circuit.
If you are uncomfortable exercising your judgment about which circuit features might matter at high speeds, try translating your gut experience at low speeds into the high-speed domain with a simple analogy. Ask yourself whether it would be reasonable to solder a 75-in.-long metal cylinder onto each of your 33-MHz bus traces. Sound ridiculous? Yes. Precisely as ridiculous, according to the laws of physics, as placing a 0.25-in. via on a 10-Gbps serial link.
Digital design, unlike politics, requires strict adherence to the laws of physics—immutable laws that you cannot legislate out of existence.