My last column converted an imperfect receiving device into an ideal termination using a constant-resistance network (Reference ). The schematic in Figure 1 extends that idea, combining a good termination with a useful equalizing function. Such circuits are useful in places where the rewards of improved circuit performance more than make up for the investment in circuit complexity; for example, at the end of a long transmission cable.
The circuit in Figure 1 is specifically tuned for driving a capacitive load. The design equations in the figure assume that you are operating at some baud rate, fb, and wish to enhance the high-frequency content of your signal by the desired ratio, GAC/GDC. In this scenario, GAC represents the gain at half the baud rate (fb/2), and GDC represents the asymptotic gain at lower frequencies. Within network a, capacitor CIN represents the unavoidable input capacitance of your receiver. Components L1 and R1 perform the equalization function. Network b (the dummy-load branch) exists solely to balance the impedance of the structure such that it equals Z0 at all frequencies. According to the general theory of constant-resistance circuits, you can use any network a, provided that you preserve the impedance relationship b=Z02/a, and the input impedance of the whole structure will still equal exactly Z0 at all frequencies. Networks a and b are known as dual circuits.
The example values in Figure 1 correspond to a 50Ω system operating at 2.5 Gbps with a target value of GAC/GDC=4. Figure 2 plots the frequency response of the circuit in Figure 1. The top trace (blue) shows the frequency response that results from removing components L1 and R1 and shorting across components C2 and R2, producing a simple constant-resistance termination with no equalization (Reference ). The bottom trace (red) shows the response of the whole circuit.
If you push fb/2 much beyond the natural cutoff, 1/(2πZ0CIN), the circuit still functions but at a progressively reduced ratio of GAC/GDC.
If you ever face a particularly hideous value of CIN, it helps to reduce the line impedance, Z0. The lower the impedance of the line, the more capacitive loading it tolerates. Alternatively, if you can afford some additional signal attenuation, you can add another resistor, R3, in parallel with CIN. The new resistor reduces the effective impedance driving CIN, thus reducing the time constant associated with its response. You compensate resistor R3 by raising the dummy-load resistor from Z0 to a new value of Z0+Z02/R3.
 Hendrik W Bode, Network Analysis and Feedback Amplifier Design, D. Van Nostrand, 1945