High-Speed Digital Design Seminar
Introduction to Black Magic, with
Dr. Howard Johnson
About this course Printable Index
An unrestricted version of this entire Collection, including all the movies, articles, and powerpoint source files for the seminars, is available on hard disk under a one-time, royalty-free license.
1. Vocabulary of Signal Integrity
High-Speed Digital Design: Opening Lecture.
HSDD Seminar (2015): 1.1-1.5.
[EE basics, management]
Definition of Signal Integrity. Relation to EMI. Purpose of Studying Signal Integrity. Overview of Program.
Vocabulary.
HSDD Seminar (2015): 1.11-1.27.
[capacitance, EE basics, inductance]
Your Schematic shows only the intended flow of signal power. Currents Form Loops. Every Loop of Current Has Inductance. Behavior of Inductance. Impedance Magnitude of Inductor. Effect of Inductor. Importance of Returning Current Path. Proximate Conductors Share Capacitance. How Capacitors Behave. Impedance Magnitude of Capacitor. Effect of Capacitor. Approximate Values of Capacitance. Practical Circuits are Littered with Parasitic Elements.
Frequency Content of Digital Signals.
HSDD Seminar (2015): 1.28-1.41.
[bandwidth, EE basics, ringing, rise time]
Data Band. Baud Interval Band (Rectangle = Step). Rising/Falling Edge Band. Frequencies That Matter for Digital Design. Meaning of "Frequency Response". Effect of Parasitics. Conceptual Frequency Response of Every PCB Trace. Relation of Knee Frequency to Circuit Performance. Effect of Shrinking Rise/Fall Time. International Technology Roadmap for Semiconductors (ITRS).
Effects of Delay.
HSDD Seminar (2015): 1.42-1.59.
[delay, layer stack]
Propagation Delay in Various Media. Example of Mixed Dielectric. Dielectric Properties of PCB Traces. Outer-Layer PCB Traces Are Faster. Distributed vs. Lumped Systems. Physical Length of Rising Edge. Pi Model of Transmission Line. Uses for The Pi Model.
Lumped-Element Crosstalk.
HSDD Seminar (2015): 1.60-1.81.
[capacitance, crosstalk, inductance]
Step Response Theory. How Resistive Loading Changes Circuit Delay. Mutual Capacitance and Mutual Inductance. Measurement of Mutual Coupling. Comparison of Inductive and Capacitive Crosstalk. A Faraday Cage Fixes Capacitive Coupling. Mutual Inductance is a Current-Flow Problem. Improving the Return Path Fixes Inductive Crosstalk. Why Many Engineers Think First About Capacitance.
Path of RF Current.
HSDD Seminar (2015): 1.82.
[inductance, returning signal current, SiLab HSDD]
Experiments at 1 and 10 MHz demonstrate the effect of circuit layout on the flow of current.
Skin and Dielectric Loss Chart.
HSDD Seminar (2015): 1.84-1.85.
[dielectric loss, skin effect]
Fibre Channel example at 1.06 Gb/s over 18 in. of FR-4 PCB trace.
2. Properties of Gates
Properties of Gates.
HSDD Seminar (2015): 2.1-2.10.
[ground bounce]
Voltage Margin Budget. SSO Noise (Ground Bounce). SSO Test Setup. Theory of Operation. How SSO Noise Affects Inputs.
Factors That Reduce Ground Bounce.
HSDD Seminar (2015): 2.8-2.17.
[differential signaling, ground bounce, power systems, split planes]
A Well-dispersed Array of Pwr/Gnd Pins. Differential Inputs. Shared Reference. Split-Power Architecture.
BGA Package Examples.
HSDD Seminar (2015): 2.18-2.21.
[chip packaging]
Plastic Ball Grid Array (PBGA). Flip-Chip. Upside-down with heat spreader.
IBIS I/O Buffer Information Specification.
HSDD Seminar (2015): 2.22-2.28.
[simulation]
Live discussion of the purpose and appropriate use of modeling software.
IBIS Simulation with Gaussian Edges.
HSDD Seminar: 2.29-2.33.
[rise time, simulation]
Simulation artifacts caused by the use of piecewise-linear (PWL) Spice sources. Presentation of Gaussian source useful for eliminating the artifacts.
3. Using Your Oscilloscope
Scope Probes and Loading.
HSDD Seminar (2015): 3.1-3.9.
[capacitance, probes]
FET-input probe. Differential Active Probe. Resistive-input probe. Input Impedance of Probes. Effect of Probe on Signal Under Test. Which Probe is Best?
Probe Ground Wire.
HSDD Seminar (2015): 3.14-3.17.
[inductance, probes]
Sensitivity to Length of Ground Wire. Using Short Ground Attachments.
4. Transmission Lines
Transmission Lines.
HSDD Seminar (2015): 4.1-4.3.
[EE basics, transmission line]
What Makes a Transmission Line?. Four Main Properties.
Characteristic Impedance.
HSDD Seminar (2015): 4.4-4.7.
[characteristic impedance, transmission line]
Response to Step Input. Ice-Cube Tray Analogy. Equivalence of Z0 and RTERM.
Example Geometries.
HSDD Seminar (2015): 4.8-4.10.
[coaxial, layout, microstrip, stripline, transmission line, twisted pair]
Relations Between Impedance and Delay.
Effects of Source and Load Impedance.
HSDD Seminar (2015): 4.11-4.17.
[termination, transmission line]
Exponential Decay. Time-Space Diagram. Ways to Achieve Signal Convergence.
Reflections.
HSDD Seminar (2015): 4.18-4.19.
[reflections, transmission line]
Reflection Function. Reflection Chart.
Un-terminated Line Examples.
HSDD Seminar (2015): 4.20-4.30.
[circuit topology, overshoot, ringing, transmission line]
Example: Source Impedance Too Low. Example: Source Impedance Too High.
Capacitive Loading of Transmission Line.
HSDD Seminar (2015): 4.31-4.34.
[capacitance, circuit topology, ringing, transmission line]
Tuned circuit analogy helps explain resonance.
5. Solid Plane Layers
How Solid Plane Layers Control Crosstalk.
HSDD Seminar (2015): 5.1-5.10.
[crosstalk, reference planes, transmission line]
Early Computers vs. Multilayer PCB. Microstrip Response to Changing Magnetic Field. Magnetic Field Animations. Do Not Give Your PCB Vendor Full Control Over H and W. How Much Crosstalk Can You Take?. Where Simulation Fails Us.
The Path of Returning Signal Current.
HSDD Seminar (2015): 5.12-5.17.
[reference planes, returning signal current, transmission line]
The High-Speed Path Can Look Pretty Strange. Distribution of High-Frequency Current Underneath a Signal Trace. What about Capacitance?. Crosstalk Versus Trace Separation Experiment. Crosstalk Over a Solid Ground Plane (waveforms). Crosstalk Over a Solid Ground Plane (graph).
Crosstalk is Directional.
HSDD Seminar (2015): 5.21-5.23.
[crosstalk, microstrip, stripline, transmission line]
Classroom demonstration.
Ground Plane Slots.
HSDD Seminar (2015): 5.24-5.32.
[crosstalk, reference planes, returning signal current, transmission line]
Traces Passing Over a Ground Plane Slot. Crosstalk From Ground Plane Slots. Connector Layout Slots. Crosstalk Versus Trace Separation Experiment. Crosstalk Over a Slotted Ground Plane (waveforms). Crosstalk Over a Slotted Ground Plane (graph). Why Wasn’t the Lower Plane Very Effective?
Multilayer Routing.
HSDD Seminar (2015): 5.33-5.42.
[crosstalk, guard trace, layout]
Power and Ground Fingers. Cross-Hatched Ground Grid. Guard Trace on a Two-Layer Board. Guard Trace on Multilayer Board (classroom demo covers slides 5.37 - 5.42).
Split Power Planes.
HSDD Seminar (2015): 5.43-5.46.
[crosstalk, layout, power systems, split planes]
Crossing a Split Power Plane Boundary. Use of Stitching Capacitors. Measuring Split-Plane Crosstalk.
Layer Transitions.
HSDD Seminar (2015): 5.47-5.49.
[layer stack, layout, reference planes]
Implications for Fast Signals. Best Way to Route the Board.
NASA Layer Stack.
HSDD Seminar (2015): 5.50-5.52.
[layer stack, layout, reference planes]
Extemporaneous discussion of NASA layer stack.
Segmenting the VCC Plane.
HSDD Seminar (2015): 5.53-5.54.
[layout, power systems, split planes]
When to do it.
6. Terminations
Overview of Termination Types.
HSDD Seminar (2015): 6.1-6.3.
[ringing, termination, transmission line]
Systems that suffer ringing benefit from termination. Over-damped circuits do not.
End Termination.
HSDD Seminar (2015): 6.4-6.15.
[circuit topology, termination]
Function of Split Termination. Design Constraints. Thevenin Equivalent Model of End Termination. Design Process. Design Solution. Reflections from a Capacitive Load. Effect of Stub Hanging Beyond End Termination.
Series Termination (Source Termination).
HSDD Seminar (2015): 6.16-6.27.
[circuit topology, termination]
Halving and Doubling of Signal Amplitude. Value of External Series Resistor. No Clock Receivers Allowed in Middle of Series-Terminated Line. What’s That Plateau?. What’s That Glitch?. Heavy Capacitive Loads on Series and End-Terminated Lines. How Close Must a Series-Terminator Be to the Driver?
Both-ends Termination.
HSDD Seminar (2015): 6.28.
[circuit topology, termination]
The Ax-Murderer Approach to Termination.
Comparison of Termination Styles.
HSDD Seminar (2015): 6.29-6.41.
[circuit topology, examples, termination]
End Termination. Series Termination. Power Dissipation. AC Termination. Transmission Line States. Dynamic Termination. Proper Design of AC Termination. Comparison of Terminations (chart). Double-series termination.
Effect of Capacitive Loads.
HSDD Seminar (2015): 6.42-6.52.
[capacitance, circuit topology, reflections]
Single Load in Middle of Line. Multiple Loads. Slowing Down the Rise Time. Adjusting the End Termination. Key Equations. Idea for Design.
Source-Terminated Bus Structures.
HSDD Seminar (2015): 6.53-6.57.
[multi drop, termination, transmission line]
PCI-Bus (ver. 2.1, 1995). Compromises in Design. Circle Bus.
Multiple Loads at End of Series-Terminated Line.
HSDD Seminar (2015): 6.59.
[capacitance, termination, transmission line]
Effect on signal risetime.
Bi-directional Termination.
HSDD Seminar (2015): 6.60.
[circuit topology, multi drop, termination]
A uni-linear structure that can reverse direction.
Risetime with Reactive Load.
HSDD Seminar (2015): 6.61-6.62.
[capacitance, circuit topology, inductance, rise time]
Capacitive load effect on risetime. Inductive bead effect on risetime.
Diode Termination.
HSDD Seminar (2015): 6.63-6.64.
[circuit topology, examples, termination]
Limitations of the approach. Examples.
Weak End-Termination.
HSDD Seminar (2015): 6.65.
[circuit topology, termination]
Terminations do not have to be perfect.
End-Termination of Differential Signals.
HSDD Seminar (2015): 6.66.
[circuit topology, differential signaling, termination]
Differential and common-mode termination concepts.
Differential Termination with Re-Biasing.
HSDD Seminar (2015): 6.67.
[circuit topology, differential signaling, termination]
Clever ways to change the DC offset of your differential signal.
Tight Coupling.
HSDD Seminar (2015): 6.68.
[differential signaling, layout]
Summary of effects (good and bad).
Right-Angle Bends.
HSDD Seminar (2015): 6.69-6.71.
[layout, reflections, transmission line]
Common sense related to feature size and uniformity.
Via Reflections.
HSDD Seminar (2015): 6.72-6.73.
[layout, reflections, transmission line]
Treating the via as a lumped capacitance. Effect of short trace stubs.
Gigabit Ethernet Examples.
HSDD Seminar (2015): 6.74-6.82.
[dielectric loss, dispersion, examples, reflections, skin effect, transmission line]
Serial interface at 1.25 Gb/s. Showing dielectric loss and skin effect. Showing effect of vias and mismatched terminations. Showing effect of both-ends termination vs. single-end.
7. Vias
Vias.
HSDD Book (1993): Chap 7.
[vias]
Chapter 7 from the book
High-Speed Digital Design: A Handbook of Black Magic was not filmed.
(pp. 249-262) Book
8. Rock-Solid Power
Inductance of Bypass Capacitor.
HSDD Seminar (2015): 8.1-8.13.
[bypass capacitors, inductance, layout, SiLab HSDD]
Electrical performance model useful for capacitor types.
Measured Data.
HSDD Seminar (2015): 8.14-8.19.
[bypass capacitors, examples, inductance, layout]
Surface-Mounted Configurations. Inductance of Surface-Mounted Layouts (table). New Surface-Mounted Packages. AVX Interdigitated Capacitor (IDC).
Arrays of Capacitors.
HSDD Seminar (2015): 8.20-8.26.
[bypass capacitors, power systems]
Modeling a Complete Power System. Dual-Value Capacitor Arrays. Choose the Smallest Package and the Biggest Value.
HSDD Seminar—Extra Material
Metastability of a Flip-Flop.
HSDD Seminar (2015).
[metastability, reliability, SiLab HSDD]
Principle of metastability. When it matters. How to mitigate it.
About This Course
High-Speed Digital Design covers the important and timely issues involving both high-speed digital design and signal integrity. Developed specifically for engineers and designers who work with high-speed digital signals, this workshop will give you the power to instantly recognize and solve many of today's high-speed design problems.
Main Topics
| probes | crosstalk | ringing | chip packaging |
| termination | circuit topology | reference planes | returning signal current |
| power systems | bypass capacitors | ||
Who should watch this course?
- Digital logic designers
- System architects
- Chip designers
- EMC specialists
- Applications engineers
- Technicians
- Printed wiring layout professionals
- Managers and sales people in the high-speed digital industry
- Anyone who works with digital logic at high speeds (20MHz to 20GHz and beyond)
This is a practical two-day seminar course. It is filled with examples, explanations, and classroom demonstrations. Anyone who works with high-speed digital signals will understand and benefit from the material presented. It presents material related to the book, High-Speed Digital Design: A Handbook of Black Magic, but treated in a different way and with different examples. The book, being 447 pages in length, obviously delves into the subject matter in greater detail. Think of the seminar as an introduction and, if you like it, get the book for on-the-job reference.
Course Outline Show me the book
How to view this course
The author recommends that you view no more than one hour at a time. It may help for you to print out the notes pages for each lecture and take written notes. The sections in the notes marked Points to Remember are not often highlighted in the lecture, but offer good opportunities for personal thought and reflection.
The three courses provide a certain degree of redundancy. Each begins with a section designed to make each attendee aware of certain basic concepts and vocabulary peculiar to that course. Where there is overlap, the author emphasizes different aspects of the core material, uses different examples, and approaches the subjects from varying angles. He recommends that you watch all three courses, all the way through, including all the extra movies.
The course materials cover much more material than could possibly be presented in the six days of lecture that we were able to film. Dr. Johnson arranged the slides with extra material to give himself the flexibility to focus on specific issues of interest to each particular class and to respond to questions. We include the full set of student materials here for your reference, even though some of those slides were not filmed. To help you keep on track, slide numbers appear on the right side of the course contents listing.
In addition to the student course materials, the Collection includes a full set of instructor materials in Powerpoint format. The instructor materials include original source artwork that may be of interest to those attempting to teach these courses. The necessary animation files, should you wish to use them independant of the lectures, are also available.